VHDL - Problem with std_logic_vector

Question

Hi, i'm coding a 4-bit binary adder with accumulator:

library ieee;
use ieee.std_logic_1164.all;

entity binadder is
    port(n,clk,sh:in bit;
     x,y:inout std_logic_vector(3 downto 0);
     co:inout bit;
     done:out bit);
end binadder;

architecture binadder of binadder is
    signal state: integer range 0 to 3;
    signal sum,cin:bit;
begin
    sum<= (x(0) xor y(0)) xor cin;
    co<= (x(0) and y(0)) or (y(0) and cin) or (x(0) and cin);

    process
    begin
     wait until clk='0';
     case state is
      when 0=>
       if(n='1') then
        state<=1;
       end if;
      when 1|2|3=>
       if(sh='1') then
        x<= sum & x(3 downto 1);
        y<= y(0) & y(3 downto 1);
        cin<=co;
       end if;
       if(state=3) then
        state<=0;
       end if;
     end case;
    end process;

    done<='1' when state=3 else '0';
end binadder;

The output :

-- Compiling architecture binadder of binadder

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(15):

No feasible entries for infix operator "xor".

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(15):

Type error resolving infix expression "xor" as type std.standard.bit.

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):

No feasible entries for infix operator "and".

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):

Bad expression in right operand of infix expression "or".

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):

No feasible entries for infix operator "and".

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):

Bad expression in left operand of infix expression "or".

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):

Bad expression in right operand of infix expression "or".

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):

Type error resolving infix expression "or" as type std.standard.bit.

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(28):

No feasible entries for infix operator "&".

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(28):

Type error resolving infix expression "&" as type ieee.std_logic_1164.std_logic_vector.

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(39):

VHDL Compiler exiting

I believe i'm not handling std_logic_vector's correctly. Please tell me how? :(

Answer 1

One of the features of VHDL is that very little functionality is provided in the base language itself. Most of it is provided by using packages. The second line of your code is an example of this (use ieee.std_logic_1164.all). This means that you are using all of the std_logic_1164 package. See here for what this package defines.

When you write code, you generally want to store your signals in either std_logic or std_logic_vector. There are two reasons for this. The first is that a std_logic can also represent values other than '0' or '1'. It can also represent 'Z' or 'X' for example. The second is that the simulators (such as modelsim that you are using) are optimised to run faster with std_logic.

As a general convention, it is good practice to always make the inputs and outputs from your entity a std_logic or std_logic_vector.

The specific problem you are having is that you are using the type bit (which is one of the very few types defined in the VHDL standard) with xor.

The simplest solution is to change the co output in your entity to be of type std_logic and to change the declaration for sum and cin to be of type std_logic.

entity binadder is
    port(n,clk,sh:in bit;
         x,y:inout std_logic_vector(3 downto 0);
         co:inout std_logic;
         done:out bit);
end binadder;

    signal sum,cin:std_logic;

A further comment is that it is generally bad practice to make your ports inout unless you have a very good reason to do so as this removes some of the strict type checking that is built into the language. The best solution is to create a signal within the entity itself and assign the signal directly to the output.

entity binadder is
    port(n,clk,sh:in bit;
         x,y:inout std_logic_vector(3 downto 0);
         co:out std_logic;
         done:out bit);
end binadder;

    signal co_int:std_logic;
 begin
    co_int<= (x(0) and y(0)) or (y(0) and cin) or (x(0) and cin);
    co <= co_int;

One final comment is that once the value of state is 1, how will it ever become 2 or 3?

Answer 2

Take a look into your logical-physical library mappings.

Check that the physical library actually has the packages dumped.

Make sure you are not using a different version of pre-compiled header with a different version of the simulator.

If nothing works, just make a local copy of ieee, compile the std_logic_1164 packages into it, move to work library and then compile your design. This has to work.