What Does *.o/.Suffixes in Makefile Mean?

Answer 1

The Makefile syntax is subtle and quick to anger. I might suggest having a look at the documentation for make, particularly the part about suffix rules.

Answer 2

The first .SUFFIXES line cleans out all knowledge of 'built-in' suffixes; the second reinstates the suffixes .f (traditionally Fortran) and .o (object files). The .DEFAULT rule is used when nothing else can be used. And the last rule compiles a .f file into a .o file using the $(FC) compiler. The @ means don't echo the command - and annoys me (I prefer to see the commands used to do the compilation).

I can't see a *.suffixes in the makefile extracts, so I can't tell you what it means.

Answer 3

The first line in your question is just a standard Makefile rule.

vpath.o: make.h config.h getopt.h gettext.h dep.h

A .o file is an object file; it's an intermediate product in between your source files and the final compiled binary. It contains compiled code, but it hasn't been linked together into a complete library or binary yet. This rule just says that vpath.o depends on make.h, config.h, etc., and each time those are changed, it should be re-compiled. The commands necessary to build vpath.o should follow on subsequent lines, indented with a tab character. (Apologies if I'm repeating stuff you already know; I wasn't sure what part of that first line you were confused about).

The .SUFFIXES doesn't refer to an actual file suffix; it's just a special kind of rule in a makefile which is used for configure "suffix rules".

Suffix rules are rules of the form .a.b, such as you see with your .f.o rule. They are a way of telling make that any time you see, say, a .f file (the source file), you can make a .o file (the target file) from it by following that rule, where $< indicates the source file and $@ represents the target file.

the .SUFFIXES "target" is a way to define which suffixes you can use in your suffix rules. When used with no prerequisites, it clears the built in list of suffixes; when used with prerequisites, it adds those to its list of known suffixes that may be used in suffix rules.

In GNU make, you can use the more powerful and more clear % to form pattern rules, like:

%.o: %.c
    gcc -c -o $@ $<

which is the equivalent of the suffix rule:

.c.o:
    gcc -c -o $@ $<

See the GNU Make documentation for more information (but which also mentions GNU extensions), or the Single Unix Specification/POSIX for the common, portable syntax.