make - specifying target name to make from command line

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Q:

make - specifying target name to make from command line

Hi,

I am looking at C makefile, and I have a question.

I know that 'make a' will make the target a, which is supposed to be defined in the makefile.

I want to know whether the target name itself can be supplied as an argument to make.

i.e. this is what I want to do:

$(target_name) is the name supplied to command 'make'. For example, 'make foo'.

and in the makefile,
$(target_name) = dependencies
command

I am not sure whether this is possible... could not find anything in the make manual too.

If anyone can help me with this, it'll be awesome.

Thanks,

+2 A:

Everything you are asking about is what make does by default - there is no need to write any special code in the makefile to do this. You seem rather confused about make (it is not particularly C related, for example). The best guide to it is the GNU Make Manual, which is not only a manual but a pretty good tutorial.

anon 2010-01-20 21:25:39

Yeah.. for example here it shows how you can specify different targets in one makefile http://www.gnu.org/software/make/manual/make.html#Rule-Introduction

littlegreen 2010-01-20 21:27:54

Thanks for the responses.Perhaps I was not clear. What I meant was, 'the target name is not predefined in the makefile.' It is supplied from command-line and used in the makefile. Is that possible?

Chaitanya 2010-01-20 22:14:31

@Chaitanya "make foo" will build the target named "foo". How can you expect it to build an undefined target?

anon 2010-01-20 22:23:39

Well it is possible to build a target not in the makefile if you are using implicit rules, for instance if you have foo.c and no makefile running `make foo` will work and compile foo.

Scott Wales 2010-01-20 23:38:40

Thanks for the clarifications!

Chaitanya 2010-01-24 16:11:29

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make - specifying target name to make from command line

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