Getting Quiet Make to echo command lines on error

Question

I have a Makefile building many C files with long long command lines and we've cleaned up the output by having rules such as:

.c${MT}.doj:

 @echo "Compiling $<";\
  $(COMPILER) $(COPTS) -c -o $@ $<

Now this is great as the @ suppresses the compilation line being emitted. But when we get an error, all we get is the error message, no command line. Can anyone think of a "neat" way to emit the command line? All I can think of doing is echoing it to a file and have a higher level make catch the error and cat the file. Hacky I know.

Answer 1

Tested and it worked (GNU make in Linux):

.c${MT}.doj:
     @echo "Compiling $<";\
          $(COMPILER) $(COPTS) -c -o $@ $<  \
          || echo "Error in command: $(COMPILER) $(COPTS) -c -o $@ $<" \
          && false

Answer 2

A simple solution would be to use a simple script abc like the following:

#!/bin/bash

$@
code=$?
if (( code )); then
  echo error running $@
fi
exit $code

Then you can write abc $(COMPILER) $(COPTS) -c -o $@ $< in your Makefile. Do note that this does not work when you have pipes or redirects (as they will be applied to abc instead of the command you want to run).

You can also just put similar code directly in the Makefile if that's preferable.

Answer 3

I recently used a utility called logtext for the likes of tracking what output had occurred during the course of a bat file executing. Check it out, you may find this pretty useful if you want to know what error occurred where.