GNU make variables in Makefile

Question

Hi,

I would like to create a Makefile which also creates a simple script for running the compiled application.

I have something like the following:

@touch $(SCRIPT)
@echo LD_LIBRARY_PATH=$(LIB_DIR) $(APP_DIR)/$(APP) $1 $2 $3 $4 $5 $6 > $(SCRIPT)
@chmod +x $(SCRIPT)
@echo Script successfully created.

And I want $1 $2 ... to appear in the script exactly like $1 $2 ... to represent scripts command-line arguments. I can't get it worked because Makefile is using $1 $2 as its own variables.. How can I accomplish that?

Answer 1

Escape the $ by doubling it:

@echo LD_LIBRARY_PATH=$(LIB_DIR) $(APP_DIR)/$(APP) $$1 $$2 $$3 $$4 $$5 $$6 > $(SCRIPT)

If you’ve got secondary expansion activated (don’t worry – you probably haven’t!) you need to double the $s again, resulting in e.g. $$$$1.

By the way, the @touch command is redundant.

Answer 2

Use double dollar sign to tell make you mean a literal $, not a variable expansion, and single-quote the whole thing to prevent further shell expansion when echoed:

@echo 'LD_LIBRARY_PATH=$(LIB_DIR) $(APP_DIR)/$(APP) $$1 $$2 $$3 $$4 $$5 $$6'