makefile internal calls to target

Question

How can I distinguish in makefile, which targets and how(when) they are called internally? I have a makefile with number of targets which are actually variables.

UPD: here is an example

build_dir := $(bin_dir)/build

xpi_built := $(build_dir)/$(install_rdf) \
             $(build_dir)/$(chrome_manifest) \
             $(chrome_jar_file) \
             $(default_prefs)/*

xpi_built_no_dir := $(subst $(build_dir)/,,$(xpi_built))

.PHONY: install
install: $(build_dir) $(xpi_built)
    @echo "Installing in profile folder: $(profile_location)"
    @cp -Rf $(build_dir)/* $(profile_location)
    @echo "Installing in profile folder. Done!"
    @echo

$(xpi_file): $(build_dir) $(xpi_built)
    @echo "Creating XPI file."
    @cd $(build_dir); $(ZIP) -r ../$(xpi_file) $(xpi_built_no_dir)
    @echo "Creating XPI file. Done!"
    @cp update.rdf $(bin_dir)/
    @cp -u *.xhtml $(bin_dir)/
    @cp -Rf $(default_prefs) $(build_dir)/; \

$(build_dir)/%: %
    cp -f $< $@

$(build_dir):

    @if [ ! -x $(build_dir) ]; \
  then \
    mkdir $(build_dir); \
  fi

Answer 1

If you specify a target on the command line, as in make clean Make will attempt to build that target. If you don't (that is, if you just run make), Make will attempt to build the default target; the default target is the first target in the makefile (in your case install) unless you set it to something else with the .DEFAULT_GOAL variable.

When Make tries to build a target, it first builds that target's prerequisites, if necessary. (When is it necessary? When a target is a file or directory that does not exist real (unless it's .PHONY, but that's an advanced topic), or when one of it's prerequisites is newer than the target (unless it's "order-only", but that's an advanced topic)). So if Make is trying to build your all, it will first try to build $(build_dir) and $(xpi_built), which have been defined elsewhere in the makefile.

If you're trying to figure out what Make will do and when, there are tricks you can use. For example, you can run make -n, and Make would tell you what it would do, instead of doing it. Or you can put a command like @echo now making $@ in a rule, to tell you what it's doing. Or for even more information:

some_target: preq another_preq and_another
    @echo Making $@. The prerequisites are $^. Of those, $? are newer than $@.
    other_commands...