Debugging Cortex M3 (ARM) Embedded - How do you tell what ISR is being run from xPSR.ISR?

Question

I am debugging a piece of firmware on an arm-family cpu (Cortex M3).

The debugger shows the CPU registers, including one called 'xPSR' which includes a sub-field called 'ISR'. The mode in the CPU registers is 'Mode=Handler", which means that the m3 cpu is in interrupt handler instead of 'thread' mode. This much I know.

I see the value for the field xPSR.ISR = 15 in there. I think that must be hexadecimal 15 (dec 21). And I am guessing that this is the "System Timer Tick 0B" interrupt from looking at the ISR vector table comments. Actually, I'm now guessing it's 15 decimal, and it's the SysTick timer interrupt handler I'm looking at.(Note that because the code is assembler one-liner default-handler case, where about 100 different asm labels land at one place, it's hard to tell from the code, who invoked the ISR.)

However, I am pretty new to Cortex M3 chips, and my knowledge of ARM7TDMI is so faded from not using it that I can't remember. And I can't find this in my docs anywhere.

Can anyone tell me how to figure this out?

Answer 1

Exception number 15 decimal is the SYSTICK interrupt on the Cortex M3.

The ARM Cortex M3 Technical Reference Manual has a table (Table 5-1 - Exception types) that lists the various interrupt numbers used by the M3.

Exception type    Position       Priority       Description
--------------    ------------   --------       ------------------------------------
Reset               1             –3 (highest)  Invoked on power up and warm reset. On first instruction, 
                                                drops to lowest priority (Thread mode). This is asynchronous.
Non-maskable Int    2             –2            Cannot be stopped or pre-empted by any exception but reset. 
                                                This is asynchronous.
Hard Fault          3             –1            All classes of Fault, when the fault cannot activate because of 
                                                priority or the Configurable Fault handler has been disabled. 
                                                This is synchronous.
Memory Management   4             Configurable  Memory Protection Unit (MPU) mismatch, including access 
                                                violation and no match. This is synchronous. This is used 
                                                even if the MPU is disabled or not present, to support the 
                                                Executable Never (XN) regions of the default memory map.
Bus Fault           5             Configurable  Pre-fetch fault, memory access fault, and other 
                                                address/memory related. This is synchronous when precise 
                                                and asynchronous when imprecise.
Usage Fault         6             Configurable  Usage fault, such as Undefined instruction executed or illegal 
                                                state transition attempt. This is synchronous.
  -                 7-10            -           Reserved
SVCall              11            Configurable  System service call with SVC instruction. This is 
                                                synchronous.
Debug Monitor       12            Configurable  Debug monitor, when not halting. This is synchronous, but 
                                                only active when enabled. It does not activate if lower priority 
                                                than the current activation.
  -                 13              -           Reserved
PendSV              14            Configurable  Pendable request for system service. This is asynchronous 
                                                and only pended by software.
SysTick             15            Configurable  System tick timer has fired. This is asynchronous.

External Interrupt  16 and above  Configurable  Asserted from outside the core, INTISR[239:0], and fed 
                                                through the NVIC (prioritized). These are all asynchronous.