How to make a Makefile shorter?

Question

Hi there,

I've got the following Makefile:

all: hello.exe hellogtk.exe hellogtktng.cs

hello.exe: hello.cs
 gmcs hello.cs

hellogtk.exe: hellogtk.cs
 gmcs -pkg:gtk-sharp-2.0 hellogtk.cs

hellogtktng.exe: hellogtktng.cs
 gmcs -pkg:gtk-sharp-2.0 hellogtktng.cs

clean:
 rm -f *.exe

I'm only starting to learn how to write Makefiles, and I feel that all this is a bit repetitive. How would Makefile pros go about doing this?

Answer 1

all: hello.exe hellogtk.exe hellogtktng.exe

%.exe: %.cs
 gmcs -pkg:gtk-sharp-2.0 $<

clean:
 rm -f *.exe

Answer 2

Here's how you can add flags to specific targets.

# An empty variable for flags (Not strictly neccessary, 
# undefined variables expand to an empty string)
GMCSFLAGS =

# The first target is made if you don't specify arguments
all: hello.exe hellogtk.exe hellogtktng.exe

# Add flags to specific files
hellogtk.exe hellogtktng.exe: GCMSFLAGS = -pkg:gtk-sharp-2.0

# A pattern rule to transform .cs to .exe
# The percent sign is substituted when looking for dependancies
%.exe:%.cs
    gmcs $(GMCSFLAGS) $<
# $() expands a variable, $< is the first dependancy in the list