makefile aliases

Question

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makefile aliases

Please explain $@ $^ in the makefile below

LIBS  = -lkernel32 -luser32 -lgdi32 -lopengl32
CFLAGS = -Wall

# (This should be the actual list of C files)
SRC=$(wildcard '*.c')

test: $(SRC)
    gcc -o $@ $^ $(CFLAGS) $(LIBS)

Answer 1

These are special variables:

$@ means the target so in your case it is test.

$^ means the names of all the prerequisites, with spaces between them. In your case its the list of all the .c files.

SRC=$(wildcard '*.c') makes use of the wildcard function to get the list of all the .c files in the directory, which is then assigned to the variable SRC.

Lets say there are two C source file foo.c and bar.c. Your makefile effectively gets expanded to:

test: foo.c bar.c
      gcc -o test foo.c bar.c -Wall -lkernel32 -luser32 -lgdi32 -lopengl32

Answer 2

SRC is equal to a wildcard function in gnu make. It is a list of files that match that path. For example, it could be

SRC=a.c b.c

For the rule, it depends on all the source files, and the target is test, so we can expand the rule as follows:

gcc -o $@   $^     $(CFLAGS) $(LIBS
gcc -o test $(SRC) $(CFLAGS) $(LIBS)

and then following up by replacing CFLAGS, LIBS and SRC with the correct expansions.

For some documentation on this, take a look at this: http://www.gnu.org/software/autoconf/manual/make/Automatic-Variables.html

Answer 3

(Just in case some of the other great explanations didn't quite hit the spot)

The "make" program allows you to use, what are called automatic variables. For every rule that it executes the action for, it parses the shell statements specified in the action, and expands any of these automatic variables that it finds. The variables expand to values in the context of the particular rule being executed at that point.

So, in your case, the rule being executed is:

test: $(SRC)

In this rule, "test" is the target, and whatever $(SRC) expands to, are the dependencies. Now, as "make" parses the following shell statement specified in the action part of the rule,

gcc -o $@ $^ $(CFLAGS) $(LIBS)

it recognizes $@ and $^ as automatic variables. $@ is expanded to the target for the current rule, and $^ is expanded to the dependencies, which is "test" and expansion of $(SRC), respectively. It executes the shell statements after the variables have been expanded. You can see the final expanded version that is executed by watching the output of "make".

$(SRC) will, in turn, expand to the result of the "make" function "wildcard". Keep in mind that the syntax for a function call in "make" is $(function param ...), and is expanded to the result of the function call, in this case the list of files with ".c" as the suffix.