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If a 32bit Operating System operated with a segmented memory model would their still be a 4GB limit?

I was reading the Intel Pentium Processor Family Developer's Manual and it states that with a Segmented memory model that it is possible map up to 64TB of memory.

"In a segmented model of memory organization, the logical address space consists of as many as 16,383 segments of up to 4 gigabytes each, or a total as large as 2^46 bytes (64 terabytes). The processor maps this 64 terabyte logical address space onto the physical address space by the address translation mechanism described in Chapter 11. Application programmers can ignore the details of this mapping. The advantage of the segmented model is that offsets within each address space are separately checked and access to each segment can be individually controlled.

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This is not a complex question. I just want to be sure I understood the text correctly. If Windows or any other OS worked in a segmented model rather than a flat model would the memory limit be 64TB?


Update:

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Intel's 3-2 3a System Documentation.


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http://pdos.csail.mit.edu/6.828/2005/readings/i386/c05.htm


The Segment Register should NOT be thought as in the traditional Real-Mode sense. The Segment Register acts as a SELECTOR for the Global Descriptor Table.

In Protected mode you use a logical address in the form A:B to address memory. As in Real Mode, A is the segment part and B is the offset within that segment. The registers in > protected mode are limited to 32 bits. 32 bits can represent any integer between 0 and 4Gb. Because B can be any value between 0 and 4Gb our segments now have a maximum size of 4Gb (Same reasoning as in real-mode). Now for the difference. In protected mode A is not an absolute value for the segment. In protected mode A is a selector. A selector represents an offset into a system table called the Global Descriptor Table (GDT). The GDT contains a list of descriptors. Each of these descriptors contains information that describes the characteristics of a segment.

The Segment Selector provides additional security that cannot be achieved with paging.

Both of these methods [Segmentation and Paging]have their advantages, but paging is much better. Segmentation is, although still usable, fast becoming obsolete as a method of memory protection and virtual memory. In fact, the x86-64 architecture requires a flat memory model (one segment with a base of 0 and a limit of 0xFFFFFFFF) for some of it's instructions to operate properly.

Segmentation is, however, totally in-built into the x86 architecture. It's impossible to get around it. So here we're going to show you how to set up your own Global Descriptor Table - a list of segment descriptors.

As mentioned before, we're going to try and set up a flat memory model. The segment's window should start at 0x00000000 and extend to 0xFFFFFFFF (the end of memory). However, there is one thing that segmentation can do that paging can't, and that's set the ring level.

-http://www.jamesmolloy.co.uk/tutorial_html/4.-The%20GDT%20and%20IDT.html

A GDT for example lists the various users their access levels and the areas of memory access:

Sample GDT Table

GDT[0] = {.base=0, .limit=0, .type=0};             
// Selector 0x00 cannot be used
GDT[1] = {.base=0, .limit=0xffffffff, .type=0x9A}; 
// Selector 0x08 will be our code
GDT[2] = {.base=0, .limit=0xffffffff, .type=0x92}; 
// Selector 0x10 will be our data
GDT[3] = {.base=&myTss, .limit=sizeof(myTss), .type=0x89}; 
// You can use LTR(0x18)

http://wiki.osdev.org/GDT_Tutorial#What_should_i_put_in_my_GDT.3F

The Paging portion is what maps to physical memory. (PAE) is what provides addtional memory up to 64GB.

So in short. The answer is no you cannot have more than 4GB of logical memory. I consider the claim for 64TB a misprint in the Intel Pentium Processor Family Developer's Manual.

+1  A: 

Edit: My answer assumes that by "4GB limit" you are referring to the maximum size of linear (virtual) address space, rather than of physical address space. As explained in the comments below, the latter is not actually limited to 4GB at all - even when using a flat memory model.


Repeating your quote, with emphasis:

the logical address space consists of as many as 16,383 segments of up to 4 gigabytes each

Now, quoting from "Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture" (PDF available here):

Internally, all the segments that are defined for a system are mapped into the processor’s linear address space.

It is this linear address space which (on 32-bit processor) is limited to 4GB. So, a segmented memory model would still be subject to the limit.

Paul Baker
Not... quite. Close enough for jazz and not far enough to warrant a -1, but later processor extensions on the Pentium line (like PAE and PSE-36 and the like) actually give you a linear address space significantly larger than 4GB. 16 times larger, in fact. Were an operating system to use segments appropriate it would be possible for a single process to have access to all that space (minus whatever the kernel reserves for itself, naturally).
JUST MY correct OPINION
PAE and PSE-36 increase the **physical** address space beyond 4GB - but **linear** (virtual) addresses are still limited to 32 bits.
Paul Baker
Not to disagree just to clarify from a Windows perspective: *"Microsoft Windows implements PAE if booted with the appropriate option, but current 32-bit desktop editions enforce the physical address space within 4GB even in PAE mode. According to Geoff Chappell, Microsoft limits 32-bit versions of Windows to 4GB due to a licensing restriction, and Microsoft Technical Fellow Mark Russinovich says that some drivers were found to be unstable when encountering physical addresses above 4GB."* - Wiki on PAE
Shiftbit
*"Because multitasking computing systems commonly define a linear address space much larger than it is economically feasible to contain all at once in physical memory, some method of “virtualizing” the linear address space is needed. This virtualization of the linear address space is handled through the processor’s paging mechanism."* - Intel 3-2 Vol3A Page 94 This quote seems to be the opposte of your statement that a linear address space on a 32bit process is limited to 4GB. It sounds like the linear address space is larger than memory is feasible.
Shiftbit
Myth: PAE increases the virtual address space beyond 4GB: http://blogs.msdn.com/b/oldnewthing/archive/2004/08/18/216492.aspx I swear the Intel documentation can be misleading.
Shiftbit
+2  A: 

Do you remember the old days? DOS on x86 in real mode with 64kb segments? FAR pointers? HMA? XMS? As the amount of memory grew, they've found ways to use more memory than processor could normally address. But it was ugly.

Sure they could use segmentation for 32 bits, but why? There was no need. When 32 bit processors appeared the 4Gb limit was more than enough, so the decision to use flat model was made.

Also, a 32bit OS can use more than 4Gb, it's the process that is limited to 4Gb address space (even 2 or 3 on windows).

ruslik
Is the process only limited because it is a flat-model? What if it was a segmented-model?
Shiftbit
@Shiftbit Don't confuse the directly addressable address range with segmented access. You can use WME to access more memory, but you still won't be able to do `char* c = malloc(5*GB)` and read any value from if directly without any wrapper.
ruslik
@Shiftbit here is a better example. How would you like to program for a processor that has 1M of 64kb segments? It would have 64Gb of address space.
ruslik
+1  A: 

AFAIK, the answer is 'not necessarily', due to other limitations of the OS. They may want to keep the maximum size of memory down well below the theoretical limit, because this could make some of the internal memory structures smaller and more performant. But I really don't know... I'm no Mark Russinovich...

Take a look at PAE. I think this is what you're talking about, but since I've graduated to 64-bit pointers, I've decided to kill the brain cells which dealt with windowing memory models with Kentucky Straight Bourbon Whiskey.

Dave Markle
I like this quote in particular from Wiki *"x86 processor hardware-architecture is augmented with additional address lines used to select the additional memory, so physical address size increases from 32 bits to 36 bits. This, theoretically, increases maximum physical memory size from 4 GB to 64 GB. The 32-bit size of the virtual address is not changed, so regular application software continues to use instructions with 32-bit addresses and (in a flat memory model) is limited to 4 gigabytes of virtual address space."*
Shiftbit
+1  A: 

The Intel's segmented model is limited to 16,384 segments. That is too small a number to really make things convenient. What would have been much nicer would have been if the system could quickly switch among two or four billion segments. That's what I would have liked to have seen, rather than a 64-bit linear space. A design that could efficiently put each allocated object into a different segment would allow for no-extra-overhead range checking on every individual allocated object, object relocation with minimal impact on running code (assuming the CPU could notice when a currently-selected segment was invalidated), etc. while only requiring object references to take half as much space in the cache as a 64-bit pointer.

supercat