Functions in Makefile

Question

Hello!

I am writing a Makefile with a lot of repetitive stuff, e.g.

debug_ifort_Linux:
        if [ $(UNAME) = Linux ]; then                           \
          $(MAKE) FC=ifort FFLAGS=$(difort) PETSC_FFLAGS="..."  \
                  TARGET=$@ LEXT="ifort_$(UNAME)" -e syst;      \
        else                                                    \
          echo $(err_arch);                                     \
          exit 1;                                               \
        fi

where the target 'syst' is defined, the variable 'UNAME' is defined (and is usually Linux, but might also by Cygwin or OSF1) and the variables 'difort' and 'err_arch' are also defined. This block of code is used very many times for different compiler targets (using a name convention of ''). Since this is a huge amount of redundant code, I would like to be able to write it in a more simple manner. E.g., I would like to do something like this:

debug_ifort_Linux:
        compile(uname,compiler,flags,petsc_flags,target,lext)

where compile could be a function doing the code above based on the arguments. Does anyone have any idea how I could accomplish this?

Answer 1

You're looking for the call function.

compile =                                                 \
        if [ $(UNAME) = $(1) ]; then                      \
          $(MAKE) FC=$(2) FFLAGS=$(3) PETSC_FFLAGS="..."  \
                  TARGET=$@ LEXT="$(4)_$(UNAME)" -e syst; \
        else                                              \
          echo $(err_arch);                               \
          exit 1;                                         \
        fi

debug_ifort_Linux:
        $(call compile,Linux,ifort,$(difort),ifort)

If you can restructure your Makefile a bit, though, you should see if you can use make's conditionals instead of sh's.

Answer 2

For working with gmake I'd recommend the excellent O'Reilly Nutshell book "Managing Projects with GNU Make" (sanitised Amazon link)

HTH

cheers,

Rob