intel

What sort of acceleration does openCV use ? How can it process so fast ?

I've been using openCV quite a bit lately and I'm amazed at how fast it can process arrays. Is it using a special type of optimization or relying on special features of the CPU ? I'm on an Intel CPU btw. ...

ICC vs GCC - Optimization and CPU architecture

Hi all, I'm interested in knowing how GCC differs from Intel's ICC in terms of the optimization levels and catering to specific processor architecture. I'm using GCC 4.1.2 20070626 and ICC v11.1 for Linux. How does ICC's optimization levels (O1 to O3) differ from GCC, if they differ at all? The ICC is able to cater specifically to dif...

What's the macro to distinguish ifort from other fortran compilers?

I'm working with Fortran code that has to work with various Fortran compilers (and is interacting with both C++ and Java code). Currently, we have it working with gfortran and g95, but I'm researching what it would take to get it working with ifort, and the first problem I'm having is figuring out how to determine in the source code whet...

Enabling and Disabling DCA

Hi all, I'm using Linux Kernel version 2.6.33 on a server with Intel Xeon X5570. I assume that Intel's DCA is already enabled on my system, because I see # dmesg | grep dca dca service started, version 1.12.1 Am I right? I would like to test the effects of with and without DCA. How can I disable DCA? Thank you. Regards, Rayne ...

Task Manager: CPU usage history

I bougth recently a server with 2 x X5550, they are quad (4 cores each) total 8 cores If I check the task manager it shows in the CPU usage history 16 diagrams, Should't it be 8 cause I have 2 processors with quad? or the diagrams maybee shows the Threads of the CPU? ...

IA-32: Pushing a byte onto a stack isn't possible on Pentium, why?

Hi, I've come to learn that you cannot push a byte directly onto the Intel Pentium's stack, can anyone explain this to me please? The reason that I've been given is because the esp register is word-addressable (or, that is the assumption in our model) and it must be an "even address". I would have assumed decrementing the value of some...

Why increased pipeline depth does not always mean increased throughput?

This is perhaps more of a discussion question, but I thought stackoverflow could be the right place to ask it. I am studying the concept of instruction pipelining. I have been taught that a pipeline's instruction throughput is increased once the number of pipeline stages is increased, but in some cases, throughput might not change. Under...

Problem: Vectorizing Code with Intel Visual FORTRAN for X64

I'm compiling my fortran90 code using Intel Visual FORTRAN on Windows Server 2003 Enterprise X64 Edition. When I compile the code for 32 bit structure and using automatic and manual vectorizing options. The code will be compiled, vectorized. And when I run it on 8 core system the compiled code uses 70% of CPU that shows me that vectorizi...

Mutli-core Processors: Does each "core" run at the full clock speed or some fraction of the full clock frequency?

Let's say you have a single (1) Intel/AMD x86-64 bit 2 GHz 8 core processor. Does each of the 8 cores all run at the full 2 GHz or, does each core run at some fraction of the full 2 GHz clock (e.g. 250 MHz)? ...

JNI call to Intel or PPC arch jnilib function differs

I am making a call from within Java to a jnilib function and get different logs on PPC and Intel. My function definitions are as follows: private native int initHandler(long vendorID, long productID); JNIEXPORT jint JNICALL Java_com_sue_protocol_SerialPortObserverThread_initHandler( JNIEnv *env, jobject obj, jlong usbVendor, jlong usbP...

Step-by-step execution for Intel AT&T assembler?

Hello everyone, I'm writing a compiler that converts source code (written in a small imperative programming language) to Intel AT&T 32-bit assembler. I tend to spend a lot of time debugging, because of nasty offset-mistakes etc. in the generated code, and I would like to know if anyone knows of a tool to "walk through" the generated as...

How do I link against Intel TBB on Mac OS X with GCC?

I can't for the life of me figure out how to compile and link against the Intel TBB library on my Mac. I've run the commercial installer and the tbbvars.sh script but I can't figure this out. I have a feeling it is something really obvious and it's just been a bit too long since I've done this kind of thing. tbb_test.cpp #include <tbb/...

Attempting to load a 64-bit application, how this CPU is not compatible with 64-bit mode

I have a Dell Studio 540, 64 bit OS Windows Home Premium. My CPU is supports Intel's virtualization technology, but I don't know how to enabled it on my machine. I saw that you can do it via the bios, but I didn't see this option when going through my BIOS. Is there another way to enabled this feature? Please let me know. I'm trying to i...

how do addressing modes work on a physical level?

I'm trying to learn this basic thing about processors that should be taught in every CS department of every university. Yet i can't find it on the net (Google doesn't help) and i can't find it in my class materials either. Do you know any good resource on how addressing modes work on a physical level? I'm particularly interested in Inte...

OpenGL/GLSL checking if shader compiled fine on intel cards

hello, i am using this code to check if my glsl shader compiled fine. glGetObjectParameterivARB(obj, GL_OBJECT_INFO_LOG_LENGTH_ARB, &infologLength); if (infologLength > 1) { int charsWritten = 0; char * const infoLog = new char[infologLength]; glGetInfoLogARB(obj, infologLength, &charsWritten, infoL...

Question about the Intel's IA-32 software developer manual

I'm studying the Intel's IA-32 software developer manual. In particular, I'm reading the following manual: http://www.intel.com/Assets/PDF/manual/253666.pdf. Let's take for example the ADD instruction. On page 79 it is written that you can add an r8 (8-bit register) to an r/m8 (8-bit register or memory location). A few rows below, it is ...

Can one construct a "good" hash function using CRC32C as a base.

Given that SSE 4.2 (Intel Core i7 & i5 parts) includes a CRC32 instruction, it seems reasonable to investigate whether one could build a faster general-purpose hash function. According to this only 16 bits of a CRC32 are evenly distributed. So what other transformation would one apply to overcome that? Update How about this? Only 16 ...

Boost binding a function taking a reference

Hi all, I am having problems compiling the following snippet int temp; vector<int> origins; vector<string> originTokens = OTUtils::tokenize(buffer, ","); // buffer is a char[] array // original loop BOOST_FOREACH(string s, originTokens) { from_string(temp, s); origins.push_back(temp); } // I'd like to use this to repl...

Intel IA-32 Assembly

I'm having a bit of difficulty converting the following java code into Intel IA-32 Assembly: class Person() { char name [8]; int age; void printName() {...} static void printAdults(Person [] list) { for(int k = 0; k < 100; k++){ if (list[k].age >= 18) { list[k].printName(); } } } } My ...

Intel Assembly Programming

class MyString{ char buf[100]; int len; boolean append(MyString str){ int k; if(this.len + str.len>100){ for(k=0; k<str.len; k++){ this.buf[this.len] = str.buf[k]; this.len ++; } return false; } return true; } } Does the above translate to: start: push ebp ; save calling ebp mov ebp, esp ; setup new ebp push esi ; ...