Is a makefile basically the same thing as a batch file?

Question

I know all about batch files and made them before, but I'm unclear on what a makefile is. It looks like a batch file. What are the similarities and diffferences?

Answer 1

No. A makefile has special rules which relate how files depend on each other. It does not necessarily execute in the order it is written.

A batch file is a sequence of commands and control statements.

Makefiles often contain the same things as batch files, but batch files do not have a direct way of indicating dependencies or provide an inferred method of processing one kind of file into another kind.

Answer 2

Makefiles list commands which are executed, but they're structured differently than a list of sequential commands. Instead they have targets and the commands to 'make' them. make then checks the listed dependencies and sees what targets it needs to update to make what you told it to. There are many implicit rules (given an *.c file make already knows how to compile it to an *.o and even build an executable!) and standard variables (e.g. CFLAGS) so you can use this to your advantage. And, contrary to the man page, you can use these implicit rules without a Makefile.

The simplest way to think about it is the makefile says how to make an 'A' given a 'B', and then you tell make what you want to do (e.g. make all) rather than how to do it. It figures out the individual steps.

• GNU make reference

Answer 3

To put a fairly abstract spin on it:

• Batch files are written in a imperative language.
• Makefiles are written in a declarative language for file processing (which is intended for and usually used for build control).

Answer 4

Very interesting question. With a shell script or batch file, you are providing your computer with a list of instructions to follow in order. It starts at the top, works down until it reaches the end, and then stops. OK, there might be function definitions, loops and gotos which change the exact order in which things happen, but largely speaking the progress through the file is linear.

Makefiles, on the other hand, provide a series of instructions on how to make certain things from certain other things. When you call make, you tell it what you want, and it analyses the instructions which it has and decides which of them it needs to execute in order to make your specified target. As a result, what happens when you call a makefile depends not just on the content of the file itself, but on what you asked it to make and what state your files are in at that point.

Two different approaches for doing two different things.

Answer 5

Not at all. They're similar in the sense that all programming languages are similar (even more so since they're both scripting), but they have very different purposes.

The purpose of makefiles is to describe how to build a project. This usually means creating rules (in a special language) that say things like:

1. whenever you see a file that ends in .c, run the program "gcc" on it to compile it into a ".o" object file.
2. whenever you have a bunch of ".o"s, link them into a ".exe".

Of course this is a simplistic description.

The main benefit of using make (the "interpreter" for the makefile language) is that you get a syntax which is purpose-built for these kinds of things. For example, make usually takes care of things like checking whether a file has changed, so that you don't compile a file that doesn't have any changes.

Answer 6

Makefiles are data for the Make program. Think of them as what the old guys did before they had XML :)

Answer 7

Similar, yes, except for the dependencies, the topological sort, the macro processing, and the expert system

If you do nothing but put shell commands in a Makefile then it is in fact a lot like a catalog of batch files, and it executes each one when its associated named target is specified.

However, it is more typical to specify a graph of dependencies in a makefile, in which case make does a topological sort of all the dependencies in order to cleverly build everything in the right order starting with the earliest prerequisites.

And to be complete, I should add that make is also a macro processor. It's oriented towards software build systems, so it provides handles on symbolic elements in its problem domain, such as the names of sources and targets.

Make contains an inference engine. All versions of make have suffix rules, some versions also implement pattern rules. When combined with your specification (typically of the files comprising a software system) the result is an expert system which will decide what needs to be compiled, linked, purchased on eBay, whatever, all depending on the data and commands you have provided.