What about Programmer "Invisible" registers?

Question

These are "Programmer Visible" x86-64 registers:

What about the invisible registers? Just now I learned that MMU registers, Interrupt Descriptor Table (IDT) uses these invisible registers. I'm learning these things in the hard way. Is there any resource (book/documentation/etc) that gives me the complete picture at once?

I am aware of the programmer visible registers and comfortable in programming with them. I just want to learn about invisible registers and their functionality. I want to get a complete picture. Where can I get this info?

EDIT:

I want to get a complete picture. Where can I get this info?

These are the two books helped me understanding these all low level details.

1. Fundamentals of Computer Organization and Design ~ Sivarama P. Dandamudi - 1 edition (2003)
2. Computer Organization and Design : The Hardware/Software Interface, 4th Edition, ~ David A. Patterson, John L. Hennessy

Answer 1

You would need to study the processor reference manual for the particular processor you're interested in. Here's the Itanium Processor Reference Manual.

Answer 2

IDT is an Interrupt Descriptor Table, which contains something like this from an abstract view, first eighteen interrupts are reserved by the processor, the next eighteen are reserved by Intel for future proofing the architecture of the chip...

Interrupt    Handler
   0         divide_by_zero_handler
   1         debug_handler
   ..           ...
   13        general_exception_handler
   14        page_fault_handler
   ..           ...
   18        machine_check_handler

In this context, the handlers are part of a toy kernel, and each of the handlers are set up at boot time, prior to user-land code being loaded. (BIOS is 16 bit code aka real mode code), kernel sets up the handlers, switches to 32bit protected mode, when any of the interrupts are issued, the appropriate handler is executed depending on the Interrupt number. For example, if interrupt 14 was generated, the kernel will execute a page_fault_handler, check if the page is dirty and reside on disk, then load that page into memory, fix up the addresses and clear the dirty bit, executes an IRET Interrupt Return instruction to continue, clearing the flags....

That is an abstract view of how IDT works...There is more complex things going on behind the scenes...depending on the architecture and type of memory management such as paged/flat/protected/virtual mode addressing schemes...

Have a look here at the Intel documentation that gives an excellent and thorough view of the Intel programming...

Edit: Back in the old days of DOS (which was 16bit code and not well, exactly memory protected), it was possible to re-route the interrupt handlers to your own handlers thus overlaying the original IDT, for an example of such an interrupt, Interrupt 9 which is the Keyboard Interrupt (BIOS interrupts in this context) using the getvect(...) and setvect(...) calls, you could also, handle some (not all of the processor interrupts, notably, IDT 0 for divide by zero)...although those BIOS interrupts were quite similar in appearance to the processor interrupts, they shared a common feature, both did have the table of interrupt vectors (as it was known back then). That was how TSR (Terminate Stay Resident) programs were able to keep re-entrant in DOS as a result of the BIOS interrupts re-routed to the TSR's handlers...