Is there any kind of standard for 8086 multiprocessing?

Question

Back when I made an 8086 emulator I noticed that there was the LOCK prefix intended for synchonization in a multiprocessor environment. Yet the only multitasking I know of for the x86 arch. involves use of the APIC which didn't come around until either the Pentiums or 486s.

Was there any kind of standard for 8086 multitasking or was it done by some manufacturer specific extensions to the instruction set and/or special ports?

By standard, I mean things like: How do you separate the 2 processors if they both use the same memory? This is impossible without some kind of way to make each processor execute a different piece of code. (or cause an interrupt on only one processor)

Answer 1

Well, I'm not an expert here, but I'll try.

Something to keep in mind: Don't think "PC" or "PC architecture". Back in the day, before the IBM PC existed (let alone a standard personal computer design), Intel wasn't making PC CPU's; it was making micro-processors. There were no exact expectations on what hardware components you could combine with an 8086. You could use it to make hardware microcontrollers, electronic calculators, avionics, and -- oh, sure -- home computers.

What the LOCK prefix does (as I remember, it's been nearly 15 years since I last looked at the Intel programmer manuals) is signaling the "bus lock" line of the microprocessor for the duration of the instruction execution. Whether that had any effect, depended on what you wired to that line! Normally, yes, the line was plugged to circuitry that would prevent other components from using any of the data lines; that's what makes a bus a "bus" (but I'm not very familiar with the details).

A source of confusion is that multitasking is not the same as multiprocessor (or should we call it multicomponent?). I don't know that anybody tried to put together a PC with two 8086's plugged to the same bus, but CPUs are not the only thing wired to the bus, even in the PC architecture. For example, The software running in the 8086 might need to lock the bus when accessing a piece of memory shared with an external input device, so the external input device could not write to it at the same time the 8086 was reading it. I imagine even an old fashion PC BIOS has a fair share of this going on.

Today's multiprocessor architectures still rely on the LOCK prefix to coordinate between different processors; but that was not the primary reason why it exists and it's not its only use.

Answer 2

How do you separate the 2 processors if they both use the same memory?

If they accessed the same memory via Intel's MULTIBUS then the LOCK prefix caused exactly that kind of serialization.

If the memory was installed locally on one processor's circuit board then the LOCK prefix would not prevent other processors from coming in over the MULTIBUS and accessing this board's memory at the same time. In this configuration the programmer would have to play other games to lock the bus (and unlock the bus after finishing the memory operation).

Answer 3

Memory access at modern Intel CPUs: CPU is conectet via FSB (Front-side bus) to NorthBridge (memory controller hub). The NorthBridge share access to the memory bus, AGP and PCI (grafic) and Internal bus for connection with SouthBridge. Check diagram:

And CPU control FSB access via several hardware pins:

• PBRI# pin is used to arbitrate for ownership of FSB.
• BRO# pin is used by the processor to request the bus.
• LOCK# pin indicate locked sequence of data transaction.

EDIT I:

For 8086 CPU sistem: When CPU must share data bus and address bus with other peripheral than this is solved with DMA 8237 controller

In multiple CPU 8086 sistems the Intel Multibus IEEE 796 bus standard is in use. Check Multibus description.

EDIT II:

8086 Multy CPU systems have global (system) memory and this memory is shared via multibus. So any CPU in system has own code and data memory and access to global memory via multibus. Wheh CPU arbitrating and transferring bus control than are here serial and paralel prioryty scheme. However ther are a lot of hardware pins to controll bus access. Bus lock is made by #LOCK pin and all other CPUs will have #BUSY pin for that time on high level.