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191

answers:

5

We are required to compile C source codes using gcc in this manner:

gcc -ansi -pedantic -Wall program.c

I'm wondering how can I 'automate' this so when I enter:

gcc program.c

It will automatically compile with the 3 switches. Is this possible?

+4  A: 

To automate the build of any number of build steps / complex parameters, you should use a makefile.

Once you have a makefile you simply need to type: make

Brian R. Bondy
Downvoted for proposing a hardcoded (and broken) Makefile when the implicit rules with `export CFLAGS=...` in the environment does precisely what Jef Ty wants. (See Scott Wales' answer).
Matt B.
@Matt B: The purpose of the makefile was simply to introduce the concept of a makefile while giving the most simple possible example that will work by typing make. Without using implicit rules. I removed the example though. It is very possible that the OP will want to do something more complex with his makefile if not today then soon.
Brian R. Bondy
+3  A: 
alias gcc="gcc -ansi -pedantic -Wall"

But as @Brian said, you really should use a makefile, or better, a build system like CMake or SCons.

Jesse Beder
I would call it something besides `gcc` so that if I ever wanted to use it in non-crazy-naggy mode I could still call `gcc`.
nategoose
+2  A: 

A makefile would be the traditional way, especially as part of a larger build process.

If you frequently want to build without a makefile, you could define an alias in your .bashrc or equivalent: alias gcc=gcc -ansi -pedantic -Wall.

JSBangs
+7  A: 

You can also use the implicit rules of make, so that you don't have to write a makefile for every program. Make will automatically call the compiler if you say make foo and there exists a foo.c file in the current directory. To add flags to this define the variable CFLAGS in your environment, e.g. in bash add export CFLAGS="-Wall -pedantic -ansi" to .bashrc.

If your program depends on multiple files however you'll have to create a makefile, but for C compilation you can get away with just listing dependancies so long as one of them has the same base name as a target.

For example for this makefile:

# Makefile
foo:foo.o bar.o

running make will execute the commands

gcc $CFLAGS -c -o foo.o foo.c
gcc $CFLAGS -c -o bar.o bar.c
gcc -o foo foo.o bar.o

without you having to add any rules.

Scott Wales
+1  A: 

You can use a shell script that takes some cues by how its called and invokes make after setting CFLAGS appropriately for the occasional one-off build.

Lets say you have /usr/bin/compile , which is a shell script that looks at $0 to see what name actually invoked it. You then make symbolic links to it named pedantic, fullwarn, etc.

In the shell script itself, something like:

OLDCFLAGS=$CFLAGS
WHATAMI=$(basename $0)

case "$WHATAMI" in
    pedantic)
        export CFLAGS="-Wall -pedantic -ansi"
        make $@
        exit $?
    ;;
    c99)
        export CFLAGS="-std=c99 ... ... ..."
        ....

Then, to compile foo.c with the extra naggy flags:

pedantic foo

This is handy, as I said for one-off builds, e.g trying to compile code that someone posted in a question, or working out how to use a new library, etc.

For anything else, just use a makefile, as others have said.

Tim Post