What is the typical interrupt latency for WinCE 6.0 on an ARM target?

Question

What is a typical interrupt latency for WinCE 6.0 on an ARM target?

(Just looking for a ballpark value for performance estimation)

Answer 1

Depends on the processor speed. Single digit to low 10's of microseconds for the ISR in most cases. See this article for a bit more depth. It covers up to 4.2. 5.0 behaves pretty much identically to 4.2. I've not specifically tested 6.0 in the same scenario, but since kernel drivers now don't require a thunk, the ISR is likely the same and the IST is probably significantly quicker. A user-mode driver is likely to match the older 4.2/5.0 results.