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I have a microprocessor with the card's chip select (CS) line tied to a 'frame' signal automatically driven by the SPI (SSP) circuit. This causes CS to go high between each byte.

The MMC/SD specs require that CS be held low in order to enter SPI mode. Does it need to be held low the entire time, or only when transmitting each byte of CMD0?

+3  A: 

At the sdcard.org site, I found various PDF specifications for SDIO. None of these seem to have an explicit timing statement which clarifies this. However, this statement does occur:

(1) SD Bus mode is selected by CMD0 (Keep Pin 1 to high during CMD0 execution).

from page 88 of SD Host Controller Simplified Specification Version 2.00. ("Pin 1" is Chip Select (CS))

Given that sentence, an SD card manufacturer would be justified in requiring that you assert CS through the entire D0..D15 bits being sent. In other words, I think you cannot use the SPI frame signal and will need a GPIO pin or similar.

Heath Hunnicutt
There is also a GPIO pin - they are combined with an `or` gate. I guess we'll have to lift a pin to test it.
Justin Love
Managed to temporarily short out frame; no immediate effect, but I can't rule it out as I try other things.
Justin Love
Found my other errors (including misconfigured SPI thanks to compiler limitation) **This card will accept intermediate highs**, but I agree with your analysis in general.
Justin Love
Very interesting news. Good job on getting it worked out. :)
Heath Hunnicutt