Need little more clarification on address lines of processor

Question

Yesterday, while I was pondering over Why can’t OS use entire 64-bits for addressing? I found another interesting thing. Lets take Intel Core 2 Duo Processor for example.

From "4.2 Alphabetical Signals Reference" of Intel Core 2 Duo Processor E8000 and E7000 Series - Datasheet I came to know that it has 36 address lines & 64 data lines. Data sheet refers address lines as A[35:3] and data lines as D[63:0].

What exactly does this imply? This is my understanding (with few unanswered questions) from above:

1. Since, there are 36 address lines. Total addressable memory is 2^36=64GB and each physical memory location (byte) is addressed by 36-bit number.
2. Since, A[2:0] is not mentioned. It implies that MMU (Paging unit to be more specific) after translating virtual address to physical address (with the help of Address tables) it only puts 33 most significant bits on address lines A[35:3]. RAM sends all 8 possible bytes (with 3 LSB, A[2:0]) i.e.. for any request in these 8 byte range. RAM sends the same 8 byte data. right? I guess this is done for efficiency purposes.
3. What happens next? I mean MMU needed 1 byte data but RAM sent 8 bytes. How is it gonna handle it?
4. Is this adress bus width been 36-bits since intel enabled PAE?
5. I'm unable to find address-bus and data-bus width in new processor datasheets (Intel® Core™ i7 Processor Extreme Edition). :( Help me!

Answer 1

The chip's byte-enable (BE) pins specify which of the bits in the 8-byte chunk are actually relevant.

To access address 0x1 you put all zeros on A[35:3] and set BE[1] (I may have the pin numbers and polarity for BE a bit wrong, but the idea is still correct).

To access bytes 0x3:0x0 you put all zeros on A[35:3] and set BE[3:0].

This should answer questions 1, 2 and 3.

Regarding question 4, it is in fact PAE that will allow you to use 36 bits of address. In later processors the same can be achieved with 64-bit mode paging.

can't help with 5...

Answer 2

About 5: The Core i7 Architecture uses 3 (On Chip) Memory Controller (for each Channel one Controller) with a width of 64-Bit for each Channel.

But of course you can no where use the 3*64 Bit because the SSE units are conected with 128-Bit lines to the L1 cache(that are of course two 64-Bit Chache lines).

The three Channels are only useful for fast prefetching of different adresses at the same time.

But on GPR's u can only use 64-Bits (because it is a 64 Bit Architecture).

The adressspace should be 36 Bits too, because for what would you need the other bits if you could never connect so much memory.