Not sure if the title makes sense... so I'll elaborate a bit.
I'm toying with this makefile that uses gcc's auto-dependency list generator.
At the same time, I wanted to keep a nice sorted directory structure that separates source, headers, and resources.
The layout's nice and simple like so
- MAIN
- src
- include
- objects
- dependencies
Now, the makefile dependency list generator atm is this:
$(DEP_PATH)%.d : $(SRC_PATH)%.c
@${CC} $(CFLAGS) -MM -c $(INCLUDE) $< > $(DEP_PATH)$*.d
include $@
The idea here being that we generate the dependency rule, then include it to the make build.
and the result for say, foo1.o is:
foo1.o: src/foo1.c include/foo1.h include/foo2.h include/foo3.h
This would work fine if I labled all my objects to be found in the main directory... however since they in /main/objects instead... the make says it can't find the rule for /main/objects/foo1.o
Now, I tried this:
@echo "$(OBJ_PATH)" > $(DEP_PATH)$*.d
@${CC} $(CFLAGS) -MM -c $(INCLUDE) $< >> $(DEP_PATH)$*.d
Which the > feeds the object path to the new/overwritten file, then concatenates the GCC auto-dependency rule generation to it... but it adds the newline between the two sets.
I tried cat'ing two separate files with said info as well... but they also get the newlines.
Is there a nice way to prepend the dependency file w/out adding the newline?
Also, if you've got any real nice tutorials on makefiles, cat, and echo, I'd really appreciate it.
Thanks for any and all responses.