resolve Makefile wildcard % inside shell function

Question

hi,

it seems that make doesn't resolve the wildcard character % before calling the shell function, in cases like this one:

%.exe: $(shell cat %.txt)
    gcc $? -o $@

if I type this on the shell:

$ make test.exe

the shell complains that it cannot find "%.txt," but I was expecting it to find "test.txt".

is there anyway to workaround that?

thanks!

Answer 1

I think you're trying to do this:

.SUFFIXES: .exe .txt
.txt.exe:
        gcc $? -o $@

Answer 2

Make foo.txt contain the dependencies for foo.exe in Makefile format:

foo.exe: foo.o bar.o baz.o

Then use an include line in your Makefile:

include foo.txt

Lastly, update your pattern rule:

%.exe:
    gcc -o $@ $^

Answer 3

Well, the usual way to load (dynamically generated) dependencies from an external file is to use include. I.e. you can fix your example, you can just add the destination(s) during your %.txt file generation. In the Makefile you can write then something like this:

DEPS = $(OBJS:.o=.txt)

-include $(DEPS)

BTW, the usually used suffix for these dependency file is %.d.

Following web site shows an intelligent approach to integrate the dependency generation in your Makefile. I.e. the dependency files are then generated and updated as needed. No need for an 'make deps' step or something like that.

Answer 4

You can use secondary expansion feature of GNU make:

$ cat Makefile
all : x.exe
.PHONY: all
.SECONDEXPANSION:
%.exe: $$(shell cat $$(basename $$(@F)).txt)
    @echo "$@ depends on $^"

$ cat x.txt 
a
b
c

$ touch a b c

$ make
x.exe depends on a b c