Mips Architecture Pipeline fowarding:
Out of ten instructions, I don't understand these two Can someone explain?
First one:
Pipeline register containing source instruction: EX/MEM
Opcode of Source instruction: Register-register ALU
Pipeline register containing destination instruction: ID/EX
Opcode of destination instruction: Register-register ALU
Destination of the forwarded result: Bottom ALU Input
Comparison(if equal then forward): EX/MEM.IR[rd]==ID/EX.IR[RT]
Second one:
Pipeline register containing source instruction: MEM/WB
Opcode of Source instruction: Register-register ALU
Pipeline register containing destination instruction: ID/EX
Opcode of destination instruction: Register-register ALU, ALU immediate, LOAD, store, BRANCH
Destination of the forwarded result: Top ALU input
Comparison(if equal then forward): MEM/WB.IR[rd]==ID/EX.IR[rs]