Kind of an extension of http://stackoverflow.com/questions/3694100/converting-to-ascii-in-c , I was wondering exactly how divisions are handled on a PIC18X.
If I perform a DIV operation, how many instructions does the compiler interpret that as? How many clock cycles will it take for the operation to complete? Is the number of clock cycles dependent on my dividend, divisor, or both?
As kind of a less important side question: What was the first CPU to include dedicated division hardware?
Normally, the number of cycles for DIV operation varies (datasheet typically provide a max cycle #). Decent compiler don't really cares how many cycles the instruction takes, but do various optimization instead (ie. division by power of 2 are handled as shifts).
You might want to check out this website for various routine for PIC.
Depend of variable length. Check Microchip web page:AN614
From AN614...
Clocks
FXD3232S 630 32 bit/32 bit -> 32.32 signed fixed point divide
FXD3232U 683 32 bit/32 bit -> 32.32 unsigned fixed point divide
FXD3231U 588 32 bit/31 bit -> 32.31 unsigned fixed point divide
FXD3131U 579 31 bit/31 bit -> 31.31 unsigned fixed point divide
FXD3224S 529 32 bit/24 bit -> 32.24 signed fixed point divide
FXD3224U 584 32 bit/24 bit -> 32.24 unsigned fixed point divide
FXD3223U 489 32 bit/23 bit -> 32.23 unsigned fixed point divide
FXD3123U 481 31 bit/23 bit -> 31.23 unsigned fixed point divide
So for 32bit/32bit is needed 630 CPU cycles.
Divides are thrown about loosly in programming these days, but I am still sensitive to them doing a lot of microcontroller projects. With a pic you already have one hand and one leg tied behind your back to start with, doing a divide is scary. I tried to do the same thing (binary to ascii decimal) on a PIC16 and it was painful. So my homebrew speedometer was either in hex or I did an ugly if-then-else tree. Free C compilers for the pic were not available at the time.
Anyway, the 8086 had a divide. The 8085 does not appear to. But the ENIAC did, and a square root it appears. Now does that alu count as a CPU to meet your "first CPU with a divide" requirement? Mechanical machines that pre-date the ENIAC could divide as well. The PDP-11 did not appear to have one. Not seeing one on the z80/8080, no on the 6502. 6800 no but 68000 yes. 8051 yes surprisingly and the 8031. Some of the older ones, 6502, 8088/86 I know in particular, had BCD math. So instead of doing your math in binary and then trying to do a bunch of divide by 10s to put in a human decimal ascii format, you do your math in bcd from the start, then it is more of a conversion to hex without the upper letters, shift right 4 and with 0xF add 0x30, and with 0xF add 0x30, repeat.