Netmf SPI master to Pic18f4550 slave synchronization problem (C18)

Question

A .NET Micro Framework device (ChipworkX in this case) sends a byte through the SPI interface to a Pic18f. Having PIE1bits.SSPIE enabled the following code is executed on interrrupt:

void high_isr (void)  
{  
     PIE1bits.SSPIE = 0;  
     PIR1bits.SSPIF = 0;// Clear interrupt flag  
     LATDbits.LATD5=1;//enables led for high interrupt activity */  
     while ( !SSPSTATbits.BF );// wait until cycle complete  
     red_byte_array[1]=SSPBUF;  
     SSPBUF = 0x00;   
     LATDbits.LATD5=0;  
     PIE1bits.SSPIE = 1;  
}  

When sending the same byte a few times, the data does not seem to be read consistently. Both master and slave are setup for clock idle low level, and data clocking on rising edge. I don't use the chip select line because it's direct communictation. Finally, the master sends data at 100Khz, while the pic is operating at 8MHz.

Any suggestions for improving/fixing this code?

Answer 1

Given that your PIC only has ( 8 MHz / 100 kHz ) 80 cycles to respond, that Delay1KTCYx() seems rather long.