views:

167

answers:

1

I need a flip flop that reacts on the edges of two different signals. Something like this:

if(rising_edge(sig1)) then
    bit <= '0';
elsif(rising_edge(sig2)) then
    bit <= '1';
end if;

Does such a flip flop exist or is there some other technique i could use? I need this to be synthesizable on a Xilinx Virtex-5 FPGA. Thanks

+3  A: 
Marty
thank you! that seems to have done the trick
bobbyb
Cool. As I mentioned, be careful with it though - I'm not 100% sure that it's synthesisable.
Marty
Also add metastability hardening if the input signals are async to the clock.
Brian Carlton
Oops - looks like I got sig1 and sig2 switched around if comparing against your code.
Marty
As you have asked for comments, the processes output_ctrl and delay_regs should have 'rst' in the sensitivity list and for describing a register you normally want it to have a async reset, therefore I would write (please remove \n with a new line):\n if rst = '1' then\n bito = '0';\n elsif rising_edge(clk) then\n if sig_rise ...\n endif;
danielpoe