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335

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+1  Q: 

VHDL: how to set a value on an inout port?

I am trying to test a VHDL component, but can't seem to get this one inout port to give me any behaviour. I've tried setting the port to everything from '1' to '-', but it still comes up as 'U' in simulation. Any sugestions what might be wrong?

A: 

You need an explicit driver to 'Z'.

Peter Mortensen  2009-10-02 17:30:14
i realise this is the case, but i dont know what it means in vhdl code
Tore  2009-10-02 17:47:01
Can you show us a snippet of the code you have?
Marty  2009-10-06 15:50:19

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