views:

447

answers:

5

Hi!

How can I run a script, which must execute before all other makefile commands? And it will be nice (but not mandatory) to the script is not executed if there is nothing to build.

I've searched SO and Google, but can't find anything.

I have this workaround:

# myscript.bat output is empty
CHEAT_ARGUMENT = (shell myscript.bat)
CFLAGS += -DCHEAT_ARGUMENT=$(CHEAT_ARGUMENT)
AFLAGS += -DCHEAT_ARGUMENT=$(CHEAT_ARGUMENT)

But it's very ugly. Is there other way to run "pre-build step" in makefile?

Sorry for lame question, I'm newbie with makefiles :)

+1  A: 

Depending on your make version, something like the following should at least avoid running dozens of times if CFLAGS and AFLAGS are evaluated dozens of times:

CHEAT_ARG := $(shell myscript)

Note the colon.

This runs exactly once. Never more than once, but also never less than once. Choose your own tradeoffs.

ndim
Won't that run anyway even if it doesn't need to? The question asks for it not to execute if there is nothing to build.
Kinopiko
Oh right. Well, at least it runs exactly once and thus never mover than once, even if there are dozens of make rules expanding CFLAGS and AFLAGS.
ndim
ndim, Thank You! This answer is the best way for me.
zxcat
+2  A: 

What you are proposing seems a bit "un-make-like". Why not just run the command in whatever makefile target you need it to go before?

Example, if you need it to run before linking foo:

foo: ${OBJS}
    my-command-goes-here
    ${CC} -o $@ ${OBJS} ${LIBS}
asveikau
Thanks for answer. Yes, I've tried this too. But I have several $(CC) and $(AS) rules (armasm use different parameters for different architectures - the binary is universal and chooses architecture-dependent code in run-time). And it's not very good idea to add "my-command" in many places. But better then my current method
zxcat
I can't run it before link, because I need it's results earlier. And I want to run it once, not on every file processing. Before any other file precessing.
zxcat
+3  A: 

You could add a special target to your Makefile and have all your build rules depend on that:

run-script:
    myscript

.o.c: run-script
     $(CC) $(CFLAGS) -o $@ $<

.o.S: run-script
     $(AS) $(AFLAGS) -o $@ $<

Depending on what your script actually does, putting it to run once in a stage before the Makefile (configure stage in autoconf terms) could make even more sense (and be less work).

ndim
It's almost the same, as asveikau suggested. The script will be executed before each file (several times).
zxcat
And autoconf will result the same as in your first answer, isn't it?
zxcat
Uhm, you are right (need more coffee). Only if you can express some proper make deps on your script you can save on invocations.
ndim
No the script will be run once at most, no matter how many other targets are made. TRY IT.
Beta
Uhm^2. Very much so indeed.
ndim
Oops.. Beta, you are right!
zxcat
A: 

Thank you for answers. ndim helped me much, asveikau. The final file is one binary executable, so I can use now something like this:

run-script:
    myscript
$(AXF_FILE): run-script $(OBJ_DIRS) $(OBJ_FILES)
    $(LINK) #......

It will run myscript once. {AXF_FILE} value depends on myscript and I must run it before. And in this case myscript runs always, not only when rebuild is needed. After, The Simplest Answer came to my mind:

all: run-script $(AXF_FILE)

That's all ;) (Of course, any target can be used instead of "all")


Edit: this method execute script after $(AXF_FILE) is calculated too. So it's possible to get wrong value of AXF_FILE. Now only the first answer by ndim works as I need.

zxcat
+2  A: 

I propose two solutions. The first mimics what NetBeans IDE generates:

CC=gcc

.PHONY: all clean

all: post-build

pre-build:
    @echo PRE

post-build: main-build
    @echo POST

main-build: pre-build
    @$(MAKE) --no-print-directory target

target: $(OBJS)
    $(CC) -o $@ $(OBJS)

clean:
    rm -f $(OBJS) target

The second one is inpired by what Eclipse IDE generates:

CC=gcc

.PHONY: all clean
.SECONDARY: main-build

all: pre-build main-build

pre-build:
    @echo PRE

post-build:
    @echo POST

main-build: target

target: $(OBJS)
    $(CC) -o $@ $(OBJS)
    @$(MAKE) --no-print-directory post-build

clean:
    rm -f $(OBJS) target

Note that in the first one, pre and post builds are always called regardless of whether the main build is determined to be up to date or not.

In the second one, the post-build step is not executed if the state of the main build is up to date. While the pre-build step is always executed in both.

Amro
pre-build doesn't have to run before main-build in the second example as there is no dependancy between them. Watch out for this if you do a parallel make.
Scott Wales