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129

answers:

6

How can I make GNU Make use a different compiler without manually editing the makefile?

+4  A: 

You can set the environment variables CC and CXX, which are used for compiling C and C++ files respectively. By default they use the values cc and g++

Michael Mrozek
If the makefile was written to use CC and CCX
anon
Setting environment doesn't override explicit values in a makefile unless you use '-e' to tell make to let it do so. It does override defaults, though - and most likely the defaults are used.
Jonathan Leffler
+10  A: 

You should be able to do something like this:

make CC=my_compiler

This is assuming whoever wrote the Makefile used the variable CC.

jonescb
Thanks. I'll accept this when the timer runs out.
Clark Gaebel
+3  A: 

If the makefile is written like most makefiles, then it uses $(CC) when it wishes to invoke the C compiler. That's what the built-in rules do, anyway. If you specify a different value for that variable, then Make will use that instead. You can provide a new value on the command line:

make CC=/usr/bin/special-cc

You can also specify that when you run configure:

./configure CC=/usr/bin/special-cc

The configuration script will incorporate the new CC value into the makefile that it generates, so you don't need to manually edit it, and you can just run make by itself thereafter (instead of giving the custom CC value on the command line every time).

Rob Kennedy
+1  A: 

Many makefiles use 'CC' to define the compiler. If yours does, you can override that variable with

make CC='/usr/bin/gcc'
ladenedge
+1  A: 

Use variables for the compiler program name.
Either pass the new definition to the make utility or set them in the environment before building.

See Using Variables in Make

Thomas Matthews
A: 

Automatically edit the makefile.

Noah Roberts