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45

answers:

1

I am trying to perform a bitwise AND on a register, as a bitmask to remove the most significant bit (which happens to be bit 16 when counting from 0). However, when I try to compile my code using gcc, it gives me the following error messages:

Assembler messages: 19: Error: relocation overflow

My guess is that this has something to do with the size of the bit mask I am applying, because when I perform the AND with two registers containing small numbers I don't encounter the same error. The code itself looks like,

.global main
main:
save    %sp, -96, %sp

clr %l1
clr     %l2
set 0xffff, %l0
set 0xaaaa8c01, %l4
set 0xff001234, %l5
set 0x13579bdf, %l6
set 0xc8b4ae32, %l7
srl %l4, 31, %l1    
srl %l0, 15, %l2
xor %l1, %l2, %l1
and %l1, 0x1, %l1
sll %l0, 1, %l0
add %l0, %l1, %l0
and %l0, 0xffff, %l0


mov 1, %g1
ta  0

If anyone could offer some insight on how to solve this problem it would be very much appreciated.

Thanks,

badPanda

+2  A: 

The most significant bit is bit 15 (in a 16-bit integer, when bits are zero based).

Michael Goldshteyn
This is for a 32 bit integer. What I meant was that the bits from 17 onwards hold zeros (and should always hold zeros) in this particular problem. Perhaps MSB was not the correct terminology?
badpanda
Do you mean 16-31 hold zeros? Which are the most significant 16 bits in a 32 bit integer. I am wondering if you are just experiencing register overflow due to one of those srl/sll instructions.
Michael Goldshteyn
Yes, that was what I meant. Sorry for the confusion (I am just learning). All of the srl/sll instructions compile and work as intended when I run them, but the last line (add %l0, 0xffff, %l0) will not.
badpanda
@badpanda as I recall, the SPARC opcodes support immidiate values up to 10 or 12 bits. If you need more, use the `load high` instruction (can't recall the exact mnemonic).
ruslik
Thanks ruslik, this ended up being the problem.
badpanda