why should I use unpacked vectors in System Verilog?

Question

Following up on this question about the difference between packed and unpacked vectors in SV, why would I ever want to use unpacked vectors?
Packed vectors have these advantages that unpacked vectors don't have:

• You can perform bit-wise operations on them
• You can perform arithmetic operations on them
• You can take slices of them
• You can copy them as a whole vector
• You can do anything you can with unpacked vectors (to the best of my knowledge)

What advantage do unpacked vectors have over packed vectors?

Answer 1

Unpacked arrays exist for several reasons.

1) Packed arrays are stored in memory as a continuous sequence of bits. Unpacked arrays can have each element stored independently which can yield greater simulation performance.

2) Unpacked arrays can be of types that aren't bit vectors. Arrays of ints, bytes, events, structs, classes, etc. can only be unpacked.

3) Most of the array manipulation methods only work on unpacked arrays.

4) Perhaps, only unpacked arrays can be assigned to using array literals. I'm not sure.

There may be other reasons.