I am simulating a digital filter, which is 4-stage.
Stages are:
- CIC
- half-band
- OSR
- 128
Input is 4 bits and output is 24 bits. I am confused about the 24 bits output.
I use MATLAB to generate a 4 bits signed sinosoid input (using SD tool), and simulated with modelsim. So the output should be also a sinosoid. The issue is the output only contains 4 different data.
For 24 bits output, shouldn't we get a 2^24-1 different data? What's the reason for this? Is it due to internal bit width?