Modelsim, an HDL simulator, allows you to specify the font used by the output. Fixed width fonts allow for more orderly output, but many fixed width fonts are not easy on the eyes. What would you recommend? I currently use Lucida Console. I've tried Inconsolata and Consolas per some recommendations, but Modelsim does not render them ...
I am simulating a digital filter, which is 4-stage. Stages are: CIC half-band OSR 128 Input is 4 bits and output is 24 bits. I am confused about the 24 bits output. I use MATLAB to generate a 4 bits signed sinosoid input (using SD tool), and simulated with modelsim. So the output should be also a sinosoid. The issue is the output o...
I am trying to test a VHDL component, but can't seem to get this one inout port to give me any behaviour. I've tried setting the port to everything from '1' to '-', but it still comes up as 'U' in simulation. Any sugestions what might be wrong? ...
Sorry for Newbish question. I am trying to learn about FPGA programming. Before I spend $1K on a FPGA board: if I just want to learn Verilog, can I run it entirely in Modelsim? (I realize there are some timing issues that only show up in actual chips; but for learning syntax / style of coding / ...)_ Thanks! ...
I have written something small in verilog: `define LW 6'b100011 `define SW 6'b101011 parameter [3:0] i_fetch = 4'b0001, decode_rr = 4'b0010, mem_addr = 4'b0100, alu_exec = 4'b1000; and i am getting this error: Error: test.v(5): (vlog-2155) Global declarations are illegal in Verilog 2001 syntax. What I am doing wrong...
Hello, My PC has 3 Gig RAM and I want to run simulation using modelsim SE6.3 but in compile time needs more than 3 Gig Ram, what should I do??? ...
The following is some modelsim code: begin tb_in_top = 0; #5 tb_in_top = 4'b0000;#5 tb_in_top = 4'b0001; #5 tb_in_top = 4'b0010;#5 tb_in_top = 4'b0011; #5 tb_in_top = 4'b0100;#5 tb_in_top = 4'b0101; #5 tb_in_top = 4'b0110;#5 tb_in_top = 4'b0111; #5 tb_in_top = 4'b1000;#5 tb_in_top = 4'b1001; #5 tb_in_top = 4...