I am a self-taught embedded developer. I mostly use AVRs programmed in C and ASM, but I have dabbled with other systems. I am looking to move onto more complex devices like CPLDs and FPGAs, but I have no idea where to start. So my one and a half questions are: Do you prefer VHDL or Verilog and why? What is a good way for one with no pr...
Hi, How do you concatenate bits in VHDL? I'm trying to use the following code: Case b0 & b1 & b2 & b3 is ... and it throws an error Thanks ...
For a university mid-term project I have to design a configurable processor, to write the code in VHDL and then synthesize it on a Spartan 3E FPGA board from Digilent. I'm a beginner so could you point me to some information about configurable processors, to some ideas related to the concept? ...
What best practices should be observed when implementing HDL code? What are the commonalities and differences when compared to more common software development fields? ...
I'm using Altera Quartus 2 to do a custom 8 bit processor and it takes forever to compile on my laptop. I'm only using simulations and making my processor in schematic (block diagram) and VHDL. Right now it takes around 10 minutes to compile, which is a pain since I'm more on the debugging phase of the project where I have to fix up the ...
Over the years I've worked on a number of microcontroller-based projects; mostly with Microchip's PICs. I've used various microcontroller simulators, and while they can be very helpful at times, I often find myself frustrated. In real life microcontrollers never exist alone and the firmware's behavior is dependent on the environment. How...
In c (embedded) a plugin can be implemented by defining a function pointer table and an address range that the module can be loaded into. This requires linker directive to allocate the space and define the location of the function table. Is there a similar mechanism in HDL / VHDL or Verilog. I guess what I am thinking is to define a b...
I'm looking for interesting online resources on FPGA development - sites, blogs, that sort of thing. What I'm after is examples of fun (and hopefully not too expensive) projects that one can try out and learn from. ...
Consider the following problem. You have a bit-string that represents the current scheduled slave in one-hot encoding. For example, "00000100" (with the leftmost bit being #7 and rightmost #0) means that slave #2 is scheduled. Now, I want to pick the next scheduled slave in a round-robin scheduling scheme, with a twist. I have a "reque...
I posted an answer to another stackoverflow question which requires some digital logic to be implemented in Verilog or VHDL so that it can be programmed into an FPGA. How would you implement the following logic diagram in Verilog, VHDL, or any other hardware description language? The numbered boxes represent bits in a field. Each field...
I have some VHDL code I'm writing for a class. However, the synthesis tool identifies cell3, cell2, and cell1 as "dead" code and it won't synthesize it. I really have no idea what's going on to cause cell 3,2,1 to be removed in synthesis; I've reviewed it some 5+ times and asked several different people and I can't find the "why". Not...
How can I simulate the behavior of a stack or a queue in VHDL? Any pointers? I had thought of using some thing like logical shift operation of bits but how to check the constraints of stack being empty or the case of stack overflow? ...
Hi I have the following code to count till 59. It starts off fine but after 31, starts to show ASCII characters like '(', '$', '#' etc., instead of numbers. Any idea where I'm going wrong? LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; entity counter is port(clk: IN STD_LOGIC; secs:OUT INTEGER RANGE 0 ...
I'm relatively new to VHDL. I'm attempting to write code to do unsigned multiplication using a combination of full adders. When compiling it passes up to the port mapping. I've resolved the errors in the first map, but all of the others give me problems. I get the same error for each: "Expression actuals in port map aspect must be stati...
Hi, After debugging my code, I've gotten to the point where the complier accepts it, but it throws a simulator exception. The main problems I've had are with initializing the temp arrays and adding the vectors at the end. The method used for adding is one I found in a reference since you can't add STD_LOGIC_VECTORs Thanks, Buzkie li...
Can anyone recommend a good book for learning VHDL? Or failing that, any good resource? ...
What's going on here? Why am I getting an 'operator argument type mismatch', and what can I do to fix it? -- -- 32-bit counter with enable and async reset -- architecture synthesis1 of counter_32bit is signal nextvalue : std_logic_vector ( 31 downto 0 ); begin -- -- combo -- nextvalue <= value + 1; -- here -- -- se...
I want a VHDL source codes website that provide a ready to use component source code. for example: full adder vhdl source code. ...
The original question was: What are some really useful but esoteric language features in VHDL that you've actually been able to employ to do useful work? The original question was deleted, and I was just answering. I think this is an interesting question, especially when you compare VHDL to other (normal) programming languages. Discla...
Is there any free program out there that can parse a collection of VHDL files and build a block diagram from them? Edit I'm looking more for a program that will build a block diagram image to go along with the documentation for the hierarchy, similar to the way javadoc builds a class diagram after parsing the documentation for a series...