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465

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2

Hi,

After debugging my code, I've gotten to the point where the complier accepts it, but it throws a simulator exception.

The main problems I've had are with initializing the temp arrays and adding the vectors at the end.

The method used for adding is one I found in a reference since you can't add STD_LOGIC_VECTORs

Thanks, Buzkie

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all;

entity signedmult is port (cand, lier: in std_logic_vector (4 downto 0); pro: out std_logic_vector (9 downto 0));

end signedmult;

architecture synth of signedmult is --temp arrays signal a,b,c,d,e: std_logic_vector(9 downto 0);

begin process (a,b,c,d,e) variable j:integer; begin

for j in 0 to 9 loop a(j) <= '0'; b(j) <= '0'; c(j) <= '0'; d(j) <= '0'; e(j) <= '0';

end loop;

end process;

process (cand, lier,a,b,c,d,e)
variable i:integer;
begin for i in 0 to 4 loop a(i) <= cand(0) and lier(i); b(i+1) <= cand(1) and lier(i); c(i+2) <= cand(2) and lier(i); d(i+3) <= cand(3) and lier(i); e(i+4) <= cand(4) and lier(i); end loop;

end process;

a(5) <= a(4); a(6) <= a(4); a(7) <= a(4); a(8) <= a(4);

b(6) <= b(5); b(7) <= b(5); b(8) <= b(5);

c(7) <= c(6); c(8) <= c(6);

d(8) <= d(7);

pro <= std_logic_vector(unsigned(a) + unsigned(b)); -- + c + d + e;

end synth;

+2  A: 

First you should remove std_logic_arith to avoid conflict with numeric_std.

Once that is done I can't see why your addition shouldn't work.

What error do you get when running?

Also, you drive your signals from multiple processes, likely getting garbage in a and b. Is that what causes the error? Try putting all assinment to your temp arrays into one process.

Hugge
removing std_logic_arith solved the problem
Buzkie
A: 

Quick, easy way:

a(9 downto 0) <= (others=>'0');
b(9 downto 0) <= (others=>'0');
rprandi