Is there any free program out there that can parse a collection of VHDL files and build a block diagram from them?
Edit I'm looking more for a program that will build a block diagram image to go along with the documentation for the hierarchy, similar to the way javadoc builds a class diagram after parsing the documentation for a series of classes.
Altera's Quartus can compile VHDL and provide you with the top-level schematic blocks, representing the VHDL signals. Ditto with Xilinx ISE. Its not open source software, but it is free to download and use.
There's nothing open-sourced anyways. A while back, I looked for something simliar for verilog designs with no success.
Mentor's HDL designer is for this purpose, but it's not free, although you can probably get a discounted student version.
As thetrus noted Quartus has an RTL viewer as well, but the quality of diagrams produced by it is pretty poor - you can't really use them for documentation. They're most useful for catching synthesis bugs.
Synplify Pro and Synplify Premier has an RTL viewer and is my preferred program of the ones I have seen. I have also seen RTL viewers in Xilinx ISE, Altera's Quartus and Mentor's HDL designer.