In an embedded application (written in C, on a 32-bit processor) with hard real-time constraints, the execution time of critical code (specially interrupts) needs to be constant. How do you insure that time variability is not introduced in the execution of the code, specifically due to the processor's caches (be it L1, L2 or L3)? Note ...
In our embedded system (using a PowerPC processor), we want to disable the processor cache. What steps do we need to take? To clarify a bit, the application in question must have as constant a speed of execution as we can make it. Variability in executing the same code path is not acceptable. This is the reason to turn off the cache. ...
What book or website would you recommend to learn about QEMU? I'd like to see some usage examples as well as how to use the APIs. ...
For a university mid-term project I have to design a configurable processor, to write the code in VHDL and then synthesize it on a Spartan 3E FPGA board from Digilent. I'm a beginner so could you point me to some information about configurable processors, to some ideas related to the concept? ...
I am looking for things like reordering of code that could even break the code in the case of a multiple processor. ...
I have a very large XML file which I need to transform into another XML file, and I would like to do this with XSLT. I am more interested in optimisation for memory, rather than optimisation for speed (though, speed would be good too!). Which Java-based XSLT processor would you recommmend for this task? Would you recommend any other w...
I want to go backwards and learn more about how compilers, processors and memory operate on my programs. I am also interested in the physics on which all of this depends. Any good references or books would be appreciated... ...
Several years ago, the 'next big thing' was clockless computers. The idea behind it was that without a clock, the processors would run significantly faster. That was then, this is now and I can't find any info on how it's been coming along or if the idea was a bust... Anyone know? For reference... http://www1.cs.columbia.edu/async/m...
I have a loop written in C++ which is executed for each element of a big integer array. Inside the loop, I mask some bits of the integer and then find the min and max values. I heard that if I use SSE instructions for these operations it will run much faster compared to a normal loop written using bitwise AND , and if-else conditions. M...
I'm writing mostly embedded code at work. We have a big long-term project that's been developed, and has several generations, and now the processor for which it was written is being discontinued and it might be impossible even to continue using processors from the same manufacturer. (The transition will be probably from TI to Renesas FPU...
I have a quad core system with third party application that once in a while spins several processes (always the same executable but several instances of it) and takes 100% of CPU time. I also have a couple of web services running on the same box (IIS and third party). The problem with the all cores being busy is that it makes this third...
I wonder if I could read or write shared int value without locking on mips cpu (especially Amazon or Danube). What I mean is if such a read or write are atomic (other thread can't interrupt them). To be clear - I don't want to prevent the race between threads, but I care if int value itself is not corrupted. Assuming that the compiler a...
Hi! I've enabled the django request processor TEMPLATE_PROCESSORS = ( "django.core.context_processors.auth", "django.core.context_processors.debug", "django.core.context_processors.i18n", "django.core.context_processors.media", "django.core.context_processors.request", ) Still i don't have to request variable available in templates. I've...
Hi All, Just wondering what the difference between a signle precision floating point operation and double precision floating operation is. I'm especially interested in practical terms in relation to video game consoles, for example does the nintendo 64 have a 64 bit processor and if it does then would that mean it was capable of double...
How do I find out if my processor is 32 bit or 64 bit (in your language of choice)? I want to know this for both Intel and AMD processors. ...
I'm looking for a way to have a precise architecture information about Xeon E5420. This processor have 4 cores and 2x6Mo cache, so 2 cores shares a 6Mo cache. I'm working on machines that have 2 processors xeon, thus have 8 cores, and looking at /proc/cpuinfo just gives me indication about which core is on which processor. Usually odd ...
Is there a way to find out which processor (either on a single system or mutliple systems) your thread is running on, using Java native threads? If not, is there any library which could help? ...
How can I determine programmatically whether my machine is an x86, x64 or an IA64? ...
Linus Torvalds used to work for a processor company called Transmeta. The processor they made was a RISC based object in the core. If I remember correctly, the idea was that the core ran an arbitrary and upgradable "processor emulation layer" (could be x86, powerpc etc), which translated the high level opcodes into the RISC core instruct...
1) How can the processor recognize the device requesting the interrupt? 2) Given the different devices are likely to require different ISR How can the pressor obtain the starting address in each case? 3) Should a device be allowed to interrupt the processor while amother interrupt is being services? 4) How should two or more simultanemen...