Configurable processor implemented on FPGA board

Question

For a university mid-term project I have to design a configurable processor, to write the code in VHDL and then synthesize it on a Spartan 3E FPGA board from Digilent. I'm a beginner so could you point me to some information about configurable processors, to some ideas related to the concept?

Answer 1

You can check out my answer for a related question. We did nearly the same, building a CPU in VHDL for a FPGA board.

Answer 2

This is just a mockup so please be aware i will clean it up

fetch instruct1,
fetch instruct2, fetch datas1
fetch instruct3, fetch datas2, process datas1
fetch instruct4, fetch datas3, process datas2, store1 datas1
fetch instruct5, fetch datas4, process datas3, store2 datas1
fetch instruct6, fetch datas5, process datas4, store3 datas1
fetch instruct7, fetch datas6, process datas5, store4 datas1
fetch instruct8, fetch datas7, process datas6, store5 datas1

basically these are the main components of a processor Part 1 ALU: Arithmetic Logic Unit (this is where draeing would come in handy) AN ALU has 2 input ports and an output port. THe 2 input ports get operated on and the result outputed. To know which instruction the ALU has to accomplish there is a control Port. Basically this is the name of the command. So if the control port has 4bits there are 16 possible instructions.

Part 2 REGISTER UNIT: This is a set of memory cells (cache memory). The contents of this memory is often transferred to the ALU's input ports.

Part3 Control Unit: This is sort of like the orchestra master of the cpu. Its job is to 1send the data to the ALU input 2Readwhich instruction needs to happen in the Instruction Registers,send those codes to the ALU control ports

Interface. This is how the RAM and other peripherals communicate with the cpu

Everytime the intruction outputs a result it has to be stored. It can be stored in RAM so a ram write must be ready once the result is ready. At the same time, a RAM read of the next instruction's inputs can occurs.And also at the same time, the next next instruction can be fetched from RAM.

Generating 1 instruction usually requires more than 1 clock cycle. Processing an in struction is analogeous to industrial production. So chain work is done.

VLIW The programming we write is linear, meaning instructions happening one after the other. But CPUs today (not ARMs though) have multiple ALU's so multiple instructions are processed at the same time.

So you have processing units chain working multiple instructions at the same time (pipeline) and you have alot of those units (superscalar)

It then becomes a question of what can/need to do to taylor your cpu architecture.

Answer 3

I did a similar project, implementing a processor with a 5-stage pipeline in VHDL.

First things first, you have to understand the architecture of how processors work. Without understand what each stange is doing and what kind of control signals you need you've got no hope of actually writing one in VHDL.

Secondly, start drawing diagrams of how instructions and data will flow through your processor (i.e. through each stage). How is each stage hooked up to each other? Where do the control signals go? Where do my inputs come from and where do my outputs go?

Once you have a solid diagram, the actual implementation in VHDL should be relatively straightforward. You can use VHDL's behaviorial modelling to essetially explain exactly what you see in the diagram.