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804

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4

I wonder if I could read or write shared int value without locking on mips cpu (especially Amazon or Danube). What I mean is if such a read or write are atomic (other thread can't interrupt them). To be clear - I don't want to prevent the race between threads, but I care if int value itself is not corrupted.

Assuming that the compiler aligns all ints at the boundaries of cpu word, it should be possible. I use gcc (g++). Tests also shows that it seems work correctly. But maybe someone knows it for sure?

+4  A: 

Depends on the operation. Having stared at enough disassembled programs in MIPS, I know that only some operations are atomic.

assignment of a new value could be 1 op or more, you'd have to look at the assembly.

eg:

x = 0; // move $a0, $0


x = 0x50000; // lui $a0, 0x0005


x = 0x50234; // lui $a0, 0x0005
             // ori $a0, 0x0234

MIPS assembley reference or here

see here to see danube and amazon are MIPS32, which my example covers, and therefore not all 32bit integer immediate can be written atomically.

see R10000 in above posting is MIPS64. Since a 32bit value would be half the register size, it could be an atomic load/write.

sfossen
what compiler did you use to compile your example?
oo_olo_oo
Isn't int value 64bit on MIPS64 platform?
oo_olo_oo
I learned MIPS assembly first by studying code, you can use gcc to generate similar code, however I do most of my checking through reverse engineering.
sfossen
My point is that loading/modifying/storing a value in MIPS is multiple steps, and because it's a limited number of steps, it won't be as easy to spot a race condition, since you're less likely to hit it. That means you can still hit it though.
sfossen
+3  A: 

Which operations? It's plausible that int a; a=42; is atomic. There's no guarantee that a= a+42; is atomic, or in any variants like with ++. Also, you have to be concerned about what the optimizer might do, say by holding an intermediate value in a register when convenient.

Charlie Martin
+5  A: 

Use gcc's builtin atomic operations and you'll get warnings if they're not supported: http://gcc.gnu.org/onlinedocs/gcc-4.1.2/gcc/Atomic-Builtins.html

It looks like combinations of addition/subtraction and testing (at least) are possible on the hardware: http://rswiki.csie.org/lxr/http/source/include/asm-mips/atomic.h

sysrqb
Definition of atomic_read() and atomic_set() seem to acknowledge that reading and writing operations are atomic.
oo_olo_oo
unless you are using atomic_read() and atomic_set(), there is no guarantee that it will be atomic.
sfossen
danube and amazon are MIPS32, R10000 is MIPS64
sfossen
+2  A: 

The question invites misleading answers.

You can only authoritatively answer "is it atomic" questions about assembly/machine language.

Any given C/C++ code fragment makes no guarantees, can vary depending on exactly which compiler (and version) you use, etc. (Unless you call some platform-specific intrinsic or whatnot that is guaranteed to compile to a known atomic machine instruction.)

Larry Gritz
I don't think its misleading since he said: "on the mips architecture" and gcc
Edison Gustavo Muenz
But the question is "which version of GCC, with which level of optimization, compiled against which libraries, using which threading model, with what executable format, ... etc.?"
Max Lybbert
He doesn't say which MIPS chip, or which version of gcc. But mainly I was commenting that any question "...in C" is barking up the wrong tree with atomics.
Larry Gritz