Which CPU architectures support Compare And Swap (CAS)?
Hi, just curious to know which CPU architectures support compare and swap atomic primitives? ...
cpu-architecture
On 32-bit CPUs, is an 'integer' type more efficient than a 'short' type?
On a 32-bit CPU, an integer is 4 bytes and a short integer is 2 bytes. If I am writing a C/C++ application that uses many numeric values that will always fit within the provided range of a short integer, is it more efficient to use 4 byte integers or 2 byte integers? I have heard it suggested that 4 byte integers are more efficient as ...
GetNativeSystemInfo and AMD Phenom; incorrect processor type?
I'm using GetNativeSystemInfo to attempt to detect the real processor type my executable is running on, so that we can properly install support libraries for that processor. The problem I'm having is that on an AMD Phenom 9850 Quad-Core 2.50 GHz processor (an x64 processor) running Windows Vista Ultimate 64 Service Pack 1, wProcessorArc...
How can I determine for which platform an executable is compiled?
I have a need to work with Windows executables which are made for x86, x64, and IA64. I'd like to programmatically figure out the platform by examining the files themselves. My target language is PowerShell but a C# example will do. Failing either of those, if you know the logic required that would be great. ...
Detecting CPU architecture (32bit / 64bit ) in scons?
Are there any 'standard' plugins for detecting the CPU architecture in scons? BTW, this question was asked already here in a more general form... just wondering if anyone has already taken the time to incorporate this information into scons. ...
Determine target architecture of binary file in Linux (library or executable)
We have an issue related to a Java application running under a (rather old) FC3 on a Advantech POS board with a Via C3 processor. The java application has several compiled shared libs that are accessed via JNI. Via C3 processor is suppossed to be i686 compatible. Some time ago after installing Ubuntu 6.10 on a MiniItx board with the sam...
Would there be any point in designing a CPU that could handle IL directly?
If I understand this correctly: Current CPU developing companies like AMD and Intel have their own API codes (the assembly language) as what they see as the 2G language on top of the Machine code (1G language) Would it be possible or desirable (performance or otherwise) to have a CPU that would perform IL handling at it's core instead...
How are interrupts handled by dual processor machines?
I have an idea of how interrupts are handled by a dual core CPU. I was wondering about how interrupt handling is implemented on a board with more than one physical processor. Is any of the interrupt responsibility determined by the physical board's configuration? Each processor must be able to handle some types of interrupts, like di...
Reading Program Counter directly
Can the program counter on Intel CPU's can be read directly (that is without 'tricks') in kernel mode or some other mode? Thanks :-). ...
Can increment of a register be used to determine the clock rate?
Can increment of a register (in a loop) be used to determine the (effective) clock rate? I've naturally assumed it can, but I was commented that Cpu's may implant Super-scalar techniques that make this kind of computation useless. Also I was told that incrementing of registers on CPU can be done in less than one clock cycle. is it true...
Any advantage of one architecture over another for array intensive computing?
I am curious to know if there exists an architecture that is quicker for handling array intensive calculations. For example; will some arbitrary C code ran on a MIPS workstation complete quicker than when ran on a x86 workstation? I suppose a better question is do some architectures have a faster FPU? I am aware that one of the newer o...
Are C++ int operations atomic on the mips architecture
I wonder if I could read or write shared int value without locking on mips cpu (especially Amazon or Danube). What I mean is if such a read or write are atomic (other thread can't interrupt them). To be clear - I don't want to prevent the race between threads, but I care if int value itself is not corrupted. Assuming that the compiler a...
L1 memory cache on Intel x86 processors
I am trying to profile and optimize algorithms and I would like to understand the specific impact of the caches on various processors. For recent Intel x86 processors (e.g. Q9300), it is very hard to find detailed information about cache structure. In particular, most web sites (including Intel.com) that post processor specs do not inc...
Setup targeting both x86 and x64?
I have a program that requires both x64 and x86 dlls (it figures out which ones it needs at run time), but when trying to create a setup, it complains: File AlphaVSS.WinXP.x64.dll' targeting 'AMD64' is not compatible with th project's target platform 'x86' File AlphaVSS.Win2003.x64.dll' targeting 'AMD64' is not compatible with th project...
Help me out on SEGMENTS of Instructions( MC68000) programming
Please can someone explain to me how i can write a short segments of instructions to move the most significant byte in register D7 to the memory location $8000. this is how i understand it, but i m not sure i am doing it write...please can you help me correct it... Lets assume that D1= 31; BTST D1, D7; MOVE.W SR, ($8000) ...
Windows Mobile 6 CPU architectures?
Does windows Mobile 6 run on multiple processor architectures? Or is it just ARM generation X? I'm asking because I want to know whether I can compile a native binary program for it and be sure that it runs on all Windows Mobile 6 devices. ...
What is a CPU thread and how is it related to logical threads in code?
I have been seeing in the literature for some of the newer CPU's such as the Intel Xeon "Nehalem-EX" as having 8 cores and 16 threads. What are they talking about here? I saw mention of this in reference so SPARCS too, surely this isn't the kind of logical threads spawned by code ? Is this hyperthreading re-named? ...
Do certain languages have intrinsic processor architectures by-design
I'm curious to know if certain languages are, by design, better suited for certain processor architectures. When I say architectures, I don't mean ARM/PPC/MIPS but more stack, accumulator, or register based architectures. For example, I can think of Forth, which is a stack architecture. Any others? ...
What part (specifically) of a native executable makes it non-portable?
This sounds like a daft question at first, but bear with me. It is common knowledge that binaries for one CPU architecture do not run on others. So for example it is impossible to run (without a compatibility layer of some kind), an x86 binary on a sparc64 chip. The instruction sets are different, so clearly that will not work. But whe...
Are Harvard architecture computers immune to arbitrary code injection and execution attacks?
Harvard architecture computers have separate code and data memories. Does this make them immune to code injection attacks (as data cannot be executed as code)? ...