In our embedded system (using a PowerPC processor), we want to disable the processor cache. What steps do we need to take? To clarify a bit, the application in question must have as constant a speed of execution as we can make it. Variability in executing the same code path is not acceptable. This is the reason to turn off the cache. ...
It's hard to search for D using Google, so I wasn't able to find a good answer: I have an old iBook G3 and I'd like to install Linux on it and use it to compile (and test) D programs written using Tango on it. Is this possible? Or hasn't anybody tried it, yet? After all the Mac port of GDC + Tango is broken in parts, too. ...
I'm trying to find a way to perform an indirect shift-left/right operation without actually using the variable shift op or any branches. The particular PowerPC processor I'm working on has the quirk that a shift-by-constant-immediate, like int ShiftByConstant( int x ) { return x << 3 ; } is fast, single-op, and superscalar, whereas...
I'm doing iPhone development on a PowerPC Mac. How do I get code signing to work properly so that I can build to my iPhone? The iPhone SDK doesn't officially support PowerPC, but with some fidgeting, it can be installed. See here. I've got the SDK installed and running fine in Xcode and the iPhone simulator works fine. However, I can't...
I have a PS3 that I've installed YDL 6.1 and SDK 3.1 on and everything seems to be working fine, as I can compile and run the examples. However, I've run into some problems with writing programs of my own. I've created a small test case that seems to pinpoint the cause of the failure. I have the following code: // mathtest.c #include <s...
Do you guys have any advices on how to cross-compile NSPR in PowerPC? I am using Linux but I shouldn't be using the redhat linux's default gcc but the Powerpc's gcc. Thanks! ...
This is a realtime MMO client, at some random point it will crash with a jump to 0, and the stack frame is unreadable. The crashreporter (and gdb) will report thead 0 crashed XC_BAD_ACCESS (SIGBUS) KERN_PROTECTION_FAILURE at 0x0000000000000000 and srr0=lr=exception address=0 How can I catch where this error occurs? ...
Hi there. I noticed with -O2 level optimization using gcc 4.1 built on IBM AIX (for use with 5.3 and 6.1) that a bunch of lwz rxxx,offsetyyy(r2) sequences are added to an inline sequence, before bctrl (calling a method or function) is done. After the register is loaded, it is never used again after the return from the method or function...
Anyone knows c++ code coverage tool usable under the following conditions: Target platform is PowerPC CPU inside Nintendo WII dev.kit, that runs custom embedded OS. The only way to exchange data with the PC is to use custom proprietary API (sorry for my NDA). Compiler is not Microsoft, not GCC, not even command line. Namely it's Metrow...
Silverlight stopped supporting PowerPC Macs after version 1.0. Will Moonlight 2.0 work on a PowerPC Mac? We are looking at writing the next generation of our product and we are considering Silverlight. However due to our existing customer base, we could not afford to cut off PowerPC Mac users at this time, and we'd like to avoid parall...
I am trying to setup a driver for an embedded PowerPC board, and the correct way to do this today is to use the OpenFirmware Device Tree datastructure (the .dtb file, compiled from a .dts file). Creating a tree is pretty easy, but how do I get my device driver to find its node and the data in it? I have not managed to find any good ref...
I'm writing a routine to flush the PowerPC750 data cache before turning it off when using write back mode. I've found the IBM application note on programming the caches which includes a flush routine, but I am confused by the example code. I think it might be a mistake in the example but thought I'd check. In Listing 2 there are two loo...
I feel extremely comfortable dealing with 32-bit PowerPC assembly code, but I am completely lost when trying to make sense of x86 code. Do any of the other common architectures like ARM, MIPS, Sparc etc have an easier than x86 instruction set? ...
I'm writing an assembler routine to handle the 0x500 external/decrementer exception in an EABI embedded PowerPC application. In my assembler routine called from the 0x500 vector point I want to use some memory to context save registers before branching to the handler function in 'C'. Because i) the exception model guarantees the previ...
I'm looking at a core dump of a (Xenon) PowerPC executable compiled with MSVC. The function I'm debugging has an op that the MSVC disassembler calls mtmsree r13. mtmsree isn't in the IBM docs for the PPC; what does this op do? It immediately follows a mfmsr and obviously it's moving something to the machine state register, but I don't ...
I'm using a PowerPC 750 and have just started experimenting with the external interrupt. I have an interrupt-driven mini program that works fine provided the data cache is off. If I turn the cache on then the PowerPC crashes on the first access to a memory-mapped peripheral after the external interrupt has fired. This surprises me bec...
Maybe the question should be, are external interrupts even vectored on the PowerPC at all? I've been looking at http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html, 'book 3', trying to figure out how the processor locates the appropriate interrupt service routine in response to an external interrupt. It seems to sugg...
I have a pretty frustrating crasher that is impacting a small subset of my users. From my analysis it seems to be isolated to PowerPC users running 10.5. When the garbage collector runs in the background, it will silently kill my application. Here's the relevant snippet from the crashlog. Exception Type: EXC_BREAKPOINT (SIGTRAP) ...
Does anybody know which version of RubyCocoa runs on this processor (if at all)? ...
I have some SIMD code in Altivec processing 32 bit integer values in parallel. In some cases I want to load the integers as little endian, in other cases as big endian (note: this choice is regardless of the native CPU endianess; it is based on what algorithm is running). Doing the actual byte swap is very easy using Altivec's permute op...