Trying to flush the PowerPC 750 data cache

Question

I'm writing a routine to flush the PowerPC750 data cache before turning it off when using write back mode.

I've found the IBM application note on programming the caches which includes a flush routine, but I am confused by the example code. I think it might be a mistake in the example but thought I'd check. In Listing 2 there are two loops which include and instruction to "move to next block". Moving to the next block is achieved by adding 0x10 to the current address. I would have expected this to be an add of 0x20 (32) since I think the cache lines are 32 bytes wide. Can anyone confirm or repudiate my thinking?!

Answer 1

You appear to be right. With their math stated at the top of the listing:

! CTR - the number of data blocks needed to fill the cache - save it in r3
!       32K (size of cache) / 32 (bytes per block) = 0x400

They always set the count register to 0x400 and it states that there are 32bytes per block a few places in that document. So following that math you would need to increment 0x20 not 0x10. As with any assembly you should definitely test it both ways in case there is some weird silicon errata of sorts.

Answer 2

Following confirmation from other SO users I e-mailed the application note's author. He agreed that 0x10 should be 0x20 and may update the note in future.