Can dynamically pluggable modules be done in VHDL?

Question

In c (embedded) a plugin can be implemented by defining a function pointer table and an address range that the module can be loaded into.

This requires linker directive to allocate the space and define the location of the function table.

Is there a similar mechanism in HDL / VHDL or Verilog.

I guess what I am thinking is to define a block of gates in an FPGA to be for my extension feature, define the ports it will interface to and later be able to load into this block the logic to perform a certain operation.

This would have to be at runtime as the FPGA is part of the communications system that the plugin will be delivered by.

Answer 1

If you are using Xilinx FPGA's, this can be supported in some of their chips.

See: Benefits of Partial Reconfiguration with Xilinx

--jeffk++

Answer 2

The feature you're looking for is orthogonal to the domain of VHDL. VHDL allows modules (entities, implemented by architectures), so in theory, yes, this can work. But in practice, it really depends on your running system.

What do you expect to gain by this? Save reconfiguration time?

If you have a sufficiently complex board with some software running, you can easily download a fresh configuration for the FPGA from some comm channel. You can also gain small performance benefits on Xilinx, by using partial reconfiguration.

Or maybe you can just create a configurable VHDL module that the software will configure in runtime to behave as required.