verilog or systemc for testbench

Question

I am assigned with the task of verifying some verilog based RTL code. Now, coding the RTL testbench using verilog seems to be very difficult (for me). So I would like to try one of the following. - Try providing a PLI interface to the RTL and thereby invoke 'C functions for testing - Using system 'C for interfacing the 'C functions

PS: I already have a extensive 'C code that was used for testing the behavioral model. I am new to the world of hardware programming. Any pointers would be greatly appreciated.

Answer 1

If you already have extensive C code that was used to test the behavioral model, then the thing to do is to just add a PLI (or DPI) interface that will allow you to call that c code from verilog.

SystemC is basically C++ with a lot of classes that allow you to model HW. I don't see how you would benefit from learning SystemC for the task you are attempting as you already have a C model available that you can test the HW against. Learning SystemC is probably overkill for what you are trying to do.

FYI. If you want to learn something that is heavily used in the industry today then I would suggest that you learn SystemVerilog. These days SystemVerilog, basically verilog with a bunch of high level software language features built in; along with "VMM", a "verification methodology" (i.e. a bunch of libraries), seems to be all the rage in hardware verification land.

Answer 2

The question is not so easy to answer without knowing your DUV (device under verification) or the C code you have. You need means to stimulate and check your design, here you probably need to translate from/to transaction level (C data structures) to/from pin level. SystemVerilog interfaces or SystemC may be an approach. I haven't used DPI/PLI interfaces yet.

To have a "state-of-the-art" testbench you should consider to use one of the testbench methodologies out there, namely VMM or OVM. They will also provide you with documentation how to get started.

Answer 3

Sounds like you should get a tool like Mentor's or Cadence's simulators that combine RTL and SystemC code under a single system. Not free, certainly, but they are the solution for that exists in practice.

The structurally correct solution you need is for the C or SystemC to call into the RTL, not the other way around. Doing this implies integrating some RTL simulator with your C program or SystemC program. It is certainly doable, but a pretty big undertaking.

Also, i think that using SystemVerilog makes a lot of sense.

Answer 4

I've used both for SystemC and System Verilog/VMM for verification, and the answer is, it depends. When I was with a startup that was on a shoestring budget trying to get their first ASIC out the door, SystemC was a natural choice because it ran on our low-budget simulator and SystemVerilog did not. With SystemC, you don't need to use the PLI or the DPI. You actually instantiate your SystemC model as a component in your testbench, which is interesting.

However, SystemC is a C++ library that does NOT have a very intuitive syntax. You should have a decent C++ background before attempting to learn the SystemC library. The books for this that are available mostly suck, except for "SystemC from the Ground Up" by David Black.

That begin said, from what I've seen, SystemC is naturally a high-level modeling language, not a verification language, and nobody with any budget to buy real simulators is using SystemC for verification anymore. From a general career development standpoint, I would use System Verilog if it is available to you. Plus, you can always use the DPI to interface to your C model for output checking, which still using generators, monitors and scoreboards written in SV/VMM.

Answer 5

You can check if the automatic free VHDL Verilog testbench generators from the http://www.questatechnologies.com is of any use for you. There are other free utilities like verilog netlist parser, RTL ( VHDL and Verilog ) uniquifie is of any use for you.