What does it mean if a task is declared with the automatic keyword in Verilog? task automatic do_things; input [31:0] number_of_things; reg [31:0] tmp_thing; begin // ... end endtask; Note: This question is mostly because I'm curious if there are any hardware programmers on the site. :) ...
I need to implement a 4-to-1 function in Veriog. The input is 4 bits, a number from 0-15. The output is a single bit, 0 or 1. Each input gives a different output and the mapping from inputs to outputs is known, but the inputs and outputs themselves are not. I want vcs to successfully optimizing the code and also have it be as short/n...
I have a "watcher" module that is currently using global hierarchies inside it. I need to instantiate a second instance of this with a second global hierarchy. Currently: module watcher; wire sig = `HIER.sig; wire bar = `HIER.foo.bar; ... endmodule watcher w; // instantiation Desired: module watcher(input base_hier); wire sig = ba...
In my day job I, and others on my team write a lot of hardware models in Verilog-AMS, a language supported primarily by commercial vendors and a few opensource simulator projects. One thing that would make supporting each others code more helpful would be a LINTER that would check our code for common problems and assist with enforcing a...
I'm maintaining a library that contains compiled objects that need to be linked into a 3rd party executable. sometimes the executable has been compiled for Solaris, sometimes as a 32bit Linux Application, sometimes its a 64bit linux application. What I'd love to do is pass one "path" to the library, and have the application then automa...
I am a self-taught embedded developer. I mostly use AVRs programmed in C and ASM, but I have dabbled with other systems. I am looking to move onto more complex devices like CPLDs and FPGAs, but I have no idea where to start. So my one and a half questions are: Do you prefer VHDL or Verilog and why? What is a good way for one with no pr...
I am trying to design a 4-bit adder subtracter in verilog. This is only the second thing I have ever written in verilog, and I don't know all the correct syntax yet. This is the module I have so far: module Question3(carryin, X, Y, Z, S, carryout, overflow); parameter n = 4; input carryin, Z; input [n-1:0]X, Y; output re...
What best practices should be observed when implementing HDL code? What are the commonalities and differences when compared to more common software development fields? ...
Over the years I've worked on a number of microcontroller-based projects; mostly with Microchip's PICs. I've used various microcontroller simulators, and while they can be very helpful at times, I often find myself frustrated. In real life microcontrollers never exist alone and the firmware's behavior is dependent on the environment. How...
In c (embedded) a plugin can be implemented by defining a function pointer table and an address range that the module can be loaded into. This requires linker directive to allocate the space and define the location of the function table. Is there a similar mechanism in HDL / VHDL or Verilog. I guess what I am thinking is to define a b...
Consider the following problem. You have a bit-string that represents the current scheduled slave in one-hot encoding. For example, "00000100" (with the leftmost bit being #7 and rightmost #0) means that slave #2 is scheduled. Now, I want to pick the next scheduled slave in a round-robin scheduling scheme, with a twist. I have a "reque...
I posted an answer to another stackoverflow question which requires some digital logic to be implemented in Verilog or VHDL so that it can be programmed into an FPGA. How would you implement the following logic diagram in Verilog, VHDL, or any other hardware description language? The numbered boxes represent bits in a field. Each field...
Suddenly, I am made to look into some verilog testbench code which heavily uses $readmemh, and $writememh. I understood that it basically read to memory and write to memory. I will be happy if you can point to some resources related to those routines. PS: I searched in google for no success. (I am very ... very new to Verilog) ...
I want to start studying Perl, specifically for checking verilog output files. Is there some tutorial that is specific to say Perl for Verilog engineers or something like that? ...
I am assigned with the task of verifying some verilog based RTL code. Now, coding the RTL testbench using verilog seems to be very difficult (for me). So I would like to try one of the following. - Try providing a PLI interface to the RTL and thereby invoke 'C functions for testing - Using system 'C for interfacing the 'C functions PS: ...
Currently I am testing some RTL, I am using ncverilog, and it is very ... very slow. I have heard that, if we use some kind of FPGA boards, then things will be faster. Is it for real? ...
I have an verilog based test-bench, interfaced to 'C source using DPI. Now using DPI I am planning to write my whole firmware. To do this I need 3 things Register Read Register Write Interrupt handler As I understand, register reads and writes are tasks that I need to export from the RTL test-bench. And Interrupt handler (I implemented...
Hello I am trying to write a task that gives a variable paddr diffrent values: module paddr1 ; task paddr1; input [10:0]paddr; input clock; @(posedge clock) begin paddr=10 #100; paddr=20; #100; paddr=30; #100; paddr=40; #100; paddr=50; #100; paddr=60; #100; paddr=70; #100; paddr=80; #100; end endtask endmodule I trie...
I need to generate pseudo-random numbers for my genetic algorithm on a Spartan-3E FPGA and i want to implement it in verilog: could you give me any pointers on this? ...
I have a simple verilog program that increments a 32 bit counter, converts the number to an ASCII string using $sformat and then pushes the string to the host machine 1 byte at a time using an FTDI FT245RL. Unfortunately Xilinx XST keeps optimizing away the string register vector. I've tried mucking around with various initialization...