verilog

Can't make sense of error in System Verilog

I tried to compile code module counter( input clk, input upSignal, input downSignal, output [7:0] count ); always_ff @(posedge clk) begin if (upSignal) count <= count + 1; else if (downSignal) count <= count - 1; end endmodule but I get the error ...

does systemverilog support linked lists?

I tried implementing a circular doubly-linked list class (with a single sentinel node) in systemverilog. The list itself seems to work as expected but ends up crashing the simulator (corrupting stack?) This led me to wonder if this is something fundamentally unsupported by the language (in terms of allocation)? SV does have a "queue" c...

How do I implement a synthesizable DPLL in Verilog?

Is there any straight forward way to implement an all digital phase lock in synthesizable Verilog? Everything (including the VCO) should be synthesized. The signals I'm looking to lock to are ~0.1-1% of the system clock frequency. I am using one that I've reconstructed from 1980's IEEE papers, but it doesn't behave as well as advertised....