does systemverilog support linked lists?

Question

I tried implementing a circular doubly-linked list class (with a single sentinel node) in systemverilog. The list itself seems to work as expected but ends up crashing the simulator (corrupting stack?)

This led me to wonder if this is something fundamentally unsupported by the language (in terms of allocation)? SV does have a "queue" construct that can be made to work in the same way (probably more efficient in both access and insertion time).

Any ideas?

Answer 1

SystemVerilog does have a queue construct. They're declared a bit like arrays, but use the $ symbol:

int myqueue[$];   // $ indicates a queue

myqueue.push_front(14);
some_int = myqueue.pop_back();

Depending how you use combinations of methods push_front(), push_back(), pop_front() and pop_back(), you can implement stacks & FIFOs and the like. A quick internet search should give you a full list of methods and declaration options.

I doubt that SystemVerilog queues are synthesizable. And I'm not 100% sure how you'd go about making a circular buffer from one without checking indices first...