Looking at some code I'm maintaining in System Verilog I see some signals that are defined like this: node [range_hi:range_lo]x; and others that are defined like this: node y[range_hi:range_lo]; I understand that x is defined as packed, while y is defined as unpacked. However, I have no idea what that means. What is the differenc...
Following up on this question about the difference between packed and unpacked vectors in SV, why would I ever want to use unpacked vectors? Packed vectors have these advantages that unpacked vectors don't have: You can perform bit-wise operations on them You can perform arithmetic operations on them You can take slices of them You can...
I have an verilog based test-bench, interfaced to 'C source using DPI. Now using DPI I am planning to write my whole firmware. To do this I need 3 things Register Read Register Write Interrupt handler As I understand, register reads and writes are tasks that I need to export from the RTL test-bench. And Interrupt handler (I implemented...
I'm trying to cheaply and accurately predict all the system-verilog dependencies for a build flow. It is ok to over-predict the dependencies and find a few verilog files that aren't sv dependencies, but I don't want to miss any dependencies. Do I actually have to parse the Verilog in order to determine all its dependencies? There are ...
Is there a TAP (Test Anything Protocol) implementation for Verilog? It would be nice because then I could use prove to check my results automatically. Update: 10/9/09: It was asked why not use assertions. Partly TAP gives me some good reporting such as number of files and number of tests. It also can be used with smolder for reportin...
for (j=0;j<k;j=j+1) begin:loop2 assign row[i+1][j][m+i:0] = {1'b0,row[i][j][m+i-1:0]}; end row is a register. It does not work as I am doing it. Can anyone please help me to fix it? Thank you very much. ...
This is for SystemVerilog. I know you can specify weights for values, or ranges of values, in the set of values that a random variable chooses from, but what if you want a nice Gaussian distribution? How do you write that kind of constraint? ...
Hardware design with VHDL or Verilog is more like programming nowadays. But, I see SO members are not so actively talking about VHDL/Verilog programming. Is there any forum dealing with hardware design with Verilog/VHDL/SystemVerilog or SystemC? ...
I am running System Verilog inside of an ASIC simulator. SV has an import/export mechanism to call C functions from SV, and for SV functions to be called from within C. I'd like to send realtime-ish (a very slow stream) data from the simulation to a charting program that I will write in Java. What is the best way to call the Java with...
SystemVerilog added packages to provide namespaces for common code pieces (functions, types, constants, etc). But since packages are not instantiated, they cannot be parameterized, so dealing with parameterized members is problematic. In practice I have found this pretty limiting since very often my custom types have some parameters di...
I tried to compile code module counter( input clk, input upSignal, input downSignal, output [7:0] count ); always_ff @(posedge clk) begin if (upSignal) count <= count + 1; else if (downSignal) count <= count - 1; end endmodule but I get the error ...
I tried implementing a circular doubly-linked list class (with a single sentinel node) in systemverilog. The list itself seems to work as expected but ends up crashing the simulator (corrupting stack?) This led me to wonder if this is something fundamentally unsupported by the language (in terms of allocation)? SV does have a "queue" c...