SystemVerilog added packages to provide namespaces for common code pieces (functions, types, constants, etc). But since packages are not instantiated, they cannot be parameterized, so dealing with parameterized members is problematic. In practice I have found this pretty limiting since very often my custom types have some parameters dictating field widths etc.
I generally deal with this by using parameters with default values and just understanding that I will need to go back change the package source code for some applications, which seems very wrong to me. But i have yet to find a way to handle this more cleanly. For example:
package my_pkg;
parameter ADDR_MSB = 7;
parameter DATA_MSB = 31;
typedef struct {
logic [ADDR_MSB:0] address;
logic [DATA_MSB:0] data;
} simple_struct_t;
endpackage
Has anyone found a cleaner way of dealing with this? I'd love to hear about it since I think packages are a very powerful addition to SV enabling safer code reuse, but this limitation is pretty severe.