Is there a Perl tutorial for Verilog engineers?

Question

I want to start studying Perl, specifically for checking verilog output files. Is there some tutorial that is specific to say Perl for Verilog engineers or something like that?

Answer 1

I don't know anything about Verilog, but if you are already familiar with another programming language, then I highly recommend Learning Perl.

You might also check out this page for later.

Answer 2

I'm not sure about parsing the output, (you'd have to be most specific about what it looks like) but there seems to be a good guide to existing Verilog-based modules which has been updated recently.

Answer 3

I'm afraid I don't know anything about Verilog either, although I note there is a Verilog Distribution on the CPAN, and it contains a lot of modules that may be relevant to your work. Doing a search on search.cpan.org may also provide some benefit.

In any case, you'll need to learn how to walk before you can run. It's excellent to have a goal when learning a new language, but the modules won't help you unless you first understand Perl's syntax and semantics.

If you're looking for a good book to learn from, then the already mentioned Learning Perl (by Stackoverflow Regular brian d foy) is excellent; grab the latest edition you can find. If you want to start learning right now, then I'd recommend downloading Perl Training Australia's Programming Perl course manual. Both resources contain many in-depth examples, links to further information, and exercises you can try to cement your knowledge.

There's also a list of recommended online tutorials on the Perl 5 wiki.

Disclosure: I'm co-author of Perl Training Australia's course manuals, and I admire brian d foy as one of the heroes of the Perl community. I'm also an occasional contributor to the Perl 5 wiki.

All the best,

Paul

Answer 4

Verilog gate-level netlist files are just text files, usually outputted from some software such as Synopsys Design Compiler, so they are well suited to being parsed by Perl.

Being simple text files, there's really nothing special about them with regards to Perl. Study any Perl tutorial that introduces you to the basics of the Perl syntax and regular expressions and what you will learn there should be easily adaptable to your Verilog related tasks. See for example: http://perldoc.perl.org/perlintro.html - for a general intro. http://perldoc.perl.org/perlretut.html - for a good regular expressions tutorial.

However, even a simple program can have many hidden faults. For example, lets say you want to print all the module names from your hierarchical Verilog netlist:

use strict;
use warnings;

my $infile = $ARGV[0] or die "$0 Usage:\n\t$0 <input verilog file>\n\n";
open(my $in_fh , '<' , $infile) or die "$0 Error: Couldn't open $infile for reading: $!\n";

while(<$in_fh>) {

    if (m/^module\s+(\S+)/) {
        print "$1\n";
    }

}

close($in_fh) or die "$0 Error: Couldn't close $infile after reading: $!\n";

Even this short example is full of potential errors: what if the module name is not on the same line as the "module" keyword? what if there is no space between the opening "(" of the module and the module name? what if there is a space (or spaces) between the beginning of the line and the "module" keyword?

You need to be aware these challenges. If all you need is a simple one-shot solution for a specific Verilog related task, a simple Perl script such as the above solution is a good solution, providing it is properly documented to warn future users of its known shortcomings.

If you need something more complex, involving more complex parsing of Verilog code, I would perhaps try to see if any of your existing tools (compiler, linter, Formal Equivalence checker, simulator, etc.) give you access to the data you need. All of these tools include mature and working Verilog parsers, optimized for speed/memory and frequently provide a Tcl-based interface for accessing the data.

Several of the people above me have recommended Verilog-Perl. I've tried it and found it to be extremely slow. If you're handling netlists over 100MB I wouldn't use this solution but your mileage may vary.

Answer 5

I believe you are looking for Verilog Perl. For a pay class on Perl for Verilog/VHDL consider this from Doulos. I second the vote for Perl Training Australia's Programming Perl course manual for learning Perl in general.

Answer 6

The Perl Intro on perldoc is the way I first learned it. It is a really fast and easy oveview of the language. All beginners who already know a programming language should start here. You can read it in about a half hour and be ready to start coding.

Answer 7

You can also download free verilog netlist parser from http://www.questatechnologies.com . There are other free utilities like VHDL and Veriog testbench generators, RTL ( VHDL and Verilog ) uniquification tool to rename all the entitities/modules and their instances in IPs/SoC/SSs. All these utilities are platform independent and you ask ask [email protected] for any help or customization.

Answer 8

You may find one in the perl section of http://pickatutorial.com