finding all dependencies in a verilog compile

Question

I'm trying to cheaply and accurately predict all the system-verilog dependencies for a build flow. It is ok to over-predict the dependencies and find a few verilog files that aren't sv dependencies, but I don't want to miss any dependencies.

Do I actually have to parse the Verilog in order to determine all its dependencies? There are tick-include preprocessor macros, but those tick-include don't seem to load all the code currently getting compiled. There is a SYSTEM_VERILOG_PATH environment variable. Do I need to parse every system verilog file in that SYSTEM_VERILOG_PATH variable in order to determine which modules are defined in which files?

Answer 1

One good way (if this is synthesizable code) is to use your synthesis tool file list (e.g. .qsf for Altera). That tends to be complete, but if it isn't, you can look at the build log for missing files that it found.

Answer 2

I know Questa has a command line option where it will generate a makefile for you with all the dependencies in it after you have compiled your design. I'm not sure if the other simulators have that.

Another option is to browse and dump your compiled library in your simulator. You probably won't get the actual filenames the modules are compiled from, but it'll be a lot easier to parse all your verilog files for the module names that show up in the compiled library.

Answer 3

From a readily compiled environment it is possible to dump the source files (e.g. Cadence -- To list source files used by the snapshot 'worklib.top:snap' % ncls -source -snapshot worklib.top:snap ) but if you are starting from scratch I am afraid there is no easy solution. I would go for the pragmatic one: have a config file with all the directories that contain .sv files and then compile everything in it. If your project has a proper file structure, you could also modularize this by supplying config files for every major block. Hope that helps.